/netbsd-current/sys/arch/evbppc/wii/ |
H A D | pic_pi.c | 53 #define WR4(reg, val) out32(reg, val) macro 60 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 67 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 84 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 93 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 94 WR4(PI_INTSR, __BIT(irq)); 116 WR4(PI_INTMR, 0); 117 WR4(PI_INTSR, ~0U);
|
/netbsd-current/sys/dev/ic/ |
H A D | bcmgenet.c | 97 #define WR4(sc, reg, val) \ macro 106 WR4(sc, GENET_MDIO_CMD, 134 WR4(sc, GENET_MDIO_CMD, 176 WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val); 181 WR4(sc, GENET_UMAC_CMD, val); 200 WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr); 201 WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32)); 202 WR4(sc, GENET_TX_DESC_STATUS(index), status); 270 WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr); 271 WR4(s [all...] |
H A D | cdnsiic.c | 90 #define WR4(sc, reg, val) \ macro 129 WR4(sc, CR_REG, 136 WR4(sc, TIME_OUT_REG, 0xff); 195 WR4(sc, CR_REG, val); 196 WR4(sc, ISR_REG, RD4(sc, ISR_REG)); 202 WR4(sc, DATA_REG, *data); 205 WR4(sc, ADDR_REG, addr); 231 WR4(sc, CR_REG, val); 232 WR4(sc, ISR_REG, RD4(sc, ISR_REG)); 233 WR4(s [all...] |
H A D | dwc_eqos.c | 117 #define WR4(sc, reg, val) \ macro 140 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 168 WR4(sc, GMAC_MAC_MDIO_DATA, val); 174 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 229 WR4(sc, GMAC_MAC_CONFIGURATION, conf); 237 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, flow); 244 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, flow); 438 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 450 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); 535 WR4(s [all...] |
H A D | dwc_wdt.c | 86 #define WR4(sc, reg, val) \ macro 116 WR4(sc, WDT_CRR, crr); 142 WR4(sc, WDT_TORR, torr); 147 WR4(sc, WDT_CR, cr);
|
/netbsd-current/sys/arch/evbppc/wii/dev/ |
H A D | wiifb.c | 126 #define WR4(sc, reg, val) \ macro 238 WR4(sc, VI_HTR0, 0x476901AD); 239 WR4(sc, VI_HTR1, 0x02EA5140); 240 WR4(sc, VI_VTO, 0x00030018); 241 WR4(sc, VI_VTE, 0x00020019); 242 WR4(sc, VI_BBOI, 0x410C410C); 243 WR4(sc, VI_BBEI, 0x40ED40ED); 247 WR4(sc, VI_HTR0, 0x476901ad); 248 WR4(sc, VI_HTR1, 0x030a4940); 249 WR4(s [all...] |
H A D | hollywood.c | 47 #define WR4(reg, val) out32(reg, val) macro 154 WR4(HW_PPCIRQMASK, pic_irqmask); 161 WR4(HW_PPCIRQMASK, pic_irqmask); 183 WR4(HW_PPCIRQFLAGS, __BIT(irq)); 194 WR4(HW_ARMIRQMASK, val); 195 WR4(HW_ARMIRQFLAGS, __BIT(irq)); 204 WR4(HW_PPCIRQMASK, 0); 205 WR4(HW_PPCIRQFLAGS, ~0U);
|
H A D | bwai.c | 84 #define WR4(sc, reg, val) \ macro 95 WR4(sc, AI_CONTROL, val | AI_CONTROL_SCRESET); 217 WR4(sc, AI_CONTROL, 0); 220 WR4(sc, AI_AIIT, blksize / 4); 226 WR4(sc, AI_CONTROL, val); 229 WR4(sc, AI_CONTROL, val); 239 WR4(sc, AI_CONTROL, 0);
|
H A D | exi.c | 92 #define WR4(sc, reg, val) \ macro 219 WR4(exi_softc, EXI_CSR(chan), val); 234 WR4(exi_softc, EXI_CSR(chan), val); 276 WR4(exi_softc, EXI_DATA(chan), val); 277 WR4(exi_softc, EXI_CR(chan), 296 WR4(exi_softc, EXI_CR(chan), 341 WR4(exi_softc, EXI_MAR(chan), ch->ch_dmamap->dm_segs[0].ds_addr); 342 WR4(exi_softc, EXI_LENGTH(chan), datalen); 343 WR4(exi_softc, EXI_CR(chan),
|
/netbsd-current/sys/arch/arm/rockchip/ |
H A D | rk_i2c.c | 126 #define WR4(sc, reg, val) \ macro 154 WR4(sc, RKI2C_CLKDIV, 161 WR4(sc, RKI2C_CON, 0); 162 WR4(sc, RKI2C_IEN, 0); 163 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 180 WR4(sc, RKI2C_IPD, val & ipdmask); 199 WR4(sc, RKI2C_CON, con); 205 WR4(sc, RKI2C_CON, con); 219 WR4(sc, RKI2C_CON, con); 225 WR4(s [all...] |
H A D | rk_emmcphy.c | 105 #define WR4(sc, reg, val) \ macro 146 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val); 151 WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val); 157 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val); 184 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val); 198 WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val); 203 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
|
H A D | rk_vop.c | 186 #define WR4(sc, reg, val) \ macro 194 WR4(sc, reg, ((uint32_t)mask << 16) | val); 248 WR4(sc, VOP_DSP_CTRL1, val); 258 WR4(sc, VOP_SYS_CTRL, val); 325 WR4(sc, VOP_WIN0_ACT_INFO, val); 331 WR4(sc, VOP_WIN0_DSP_INFO, val); 339 WR4(sc, VOP_WIN0_DSP_ST, val); 341 WR4(sc, VOP_WIN0_COLOR_KEY, 0); 354 WR4(sc, VOP_WIN0_CTRL, val); 374 WR4(s [all...] |
H A D | rk_i2s.c | 166 #define WR4(sc, reg, val) \ macro 202 WR4(sc, I2S_CKR, ckr); 212 WR4(sc, I2S_TXCR, txcr); 223 WR4(sc, I2S_RXCR, rxcr); 260 WR4(sc, I2S_XFER, val); 269 WR4(sc, I2S_INTCR, val); 299 WR4(sc, I2S_XFER, val); 304 WR4(sc, I2S_INTCR, val); 308 WR4(sc, I2S_CLR, val); 330 WR4(s [all...] |
/netbsd-current/sys/arch/arm/ti/ |
H A D | ti_wdt.c | 90 #define WR4(sc, reg, val) \ macro 123 WR4(sc, WDT_WDSC, val); 137 WR4(sc, WDT_WSPR, 0xaaaa); 139 WR4(sc, WDT_WSPR, 0x5555); 146 WR4(sc, WDT_WSPR, 0xbbbb); 148 WR4(sc, WDT_WSPR, 0x4444); 176 WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV)); 177 WR4(sc, WDT_WLDR, counter_val); 178 WR4(sc, WDT_WCRR, counter_val); 195 WR4(s [all...] |
H A D | ti_rng.c | 66 #define WR4(sc, reg, val) \ macro 104 WR4(sc, TRNG_CONFIG_REG, 107 WR4(sc, TRNG_CONTROL_REG, 137 WR4(sc, TRNG_INTACK_REG, TRNG_INTACK_READY);
|
H A D | ti_usbtll.c | 99 #define WR4(sc, reg, val) \ macro 122 WR4(sc, USBTLL_CHANNEL_CONF(port), val); 131 WR4(sc, USBTLL_SYSCONFIG, USBTLL_SYSCONFIG_SOFTRESET); 153 WR4(sc, USBTLL_SYSCONFIG, val); 159 WR4(sc, USBTLL_SHARED_CONF, val);
|
H A D | ti_gpio.c | 141 #define WR4(sc, reg, val) \ macro 162 WR4(sc, GPIO_OE, oe); 254 WR4(sc, data_reg, data_mask); 274 WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask); 276 WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask); 327 WR4(sc, GPIO_LEVELDETECT0, val); 334 WR4(sc, GPIO_LEVELDETECT1, val); 341 WR4(sc, GPIO_RISINGDETECT, val); 348 WR4(sc, GPIO_FALLINGDETECT, val); 353 WR4(s [all...] |
H A D | ti_omaptimer.c | 108 #define WR4(sc, reg, val) \ macro 119 WR4(sc, TIMER_TISR, OVF_IT_FLAG); 143 WR4(sc, TIMER_TIER, OVF_EN_FLAG); 158 WR4(sc, TIMER_TLDR, value); 159 WR4(sc, TIMER_TCRR, value); 160 WR4(sc, TIMER_TIER, 0); 161 WR4(sc, TIMER_TCLR, TCLR_ST | TCLR_AR);
|
H A D | ti_dpll_clock.c | 135 #define WR4(sc, space, val) \ macro 272 WR4(sc, REG_CONTROL, control); 279 WR4(sc, REG_MULT_DIV1, mult_div1); 283 WR4(sc, REG_CONTROL, control); 312 WR4(sc, REG_CONTROL, control); 318 WR4(sc, REG_MULT_DIV1, mult_div1); 322 WR4(sc, REG_CONTROL, control);
|
H A D | ti_lcdc.c | 113 WR4(sc, LCD_LCDDMA_FB0_BASE, paddr); 114 WR4(sc, LCD_LCDDMA_FB0_CEILING, paddr + psize - 1); 190 WR4(sc, LCD_CTRL, val); 196 WR4(sc, LCD_RASTER_TIMING_0, val); 202 WR4(sc, LCD_RASTER_TIMING_1, val); 214 WR4(sc, LCD_RASTER_TIMING_2, val); 219 WR4(sc, LCD_LCDDMA_CTRL, val); 227 WR4(sc, LCD_RASTER_CTRL, val); 269 WR4(sc, LCD_CLKC_ENABLE, CLKC_ENABLE_DMA | CLKC_ENABLE_CORE); 270 WR4(s [all...] |
/netbsd-current/sys/arch/arm/sunxi/ |
H A D | sun8i_codec.c | 131 #define WR4(sc, reg, val) \ macro 263 WR4(sc, AIF1CLK_CTRL, val); 295 WR4(sc, HMIC_CTRL1, val); 349 WR4(sc, HMIC_STS, val); 427 WR4(sc, SYSCLK_CTL, val); 428 WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC); 429 WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC); 432 WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA); 433 WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD); 439 WR4(s [all...] |
H A D | sunxi_thermal.c | 340 #define WR4(sc, reg, val) \ macro 360 WR4(sc, THS_CALIB0, calib[0]); 362 WR4(sc, THS_CALIB1, calib[1]); 366 WR4(sc, THS_CTRL1, ADC_CALI_EN); 367 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time); 368 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT); 371 WR4(sc, THS_FILTER, sc->conf->filter); 374 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); 375 WR4(sc, THS_INTC, sc->conf->intc | SHUT_INT_ALL | ALARM_INT_ALL); 378 WR4(s [all...] |
/netbsd-current/sys/dev/fdt/ |
H A D | dwc3_fdt.c | 92 #define WR4(sc, reg, val) \ macro 95 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 97 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 158 WR4(sc, DWC3_GUSB2PHYCFG(0), val); 166 WR4(sc, DWC3_GUSB3PIPECTL(0), val); 172 WR4(sc, DWC3_GUCTL1, val); 191 WR4(sc, DWC3_DCFG, val); 202 WR4(sc, DWC3_GCTL, val);
|
/netbsd-current/sys/arch/arm/samsung/ |
H A D | exynos_uart.c | 111 #define WR4(sc, reg, val) \ macro 276 WR4(sc, SSCOM_UFCON, 285 WR4(sc, SSCOM_UCON, ucon); 289 WR4(sc, SSCOM_UCON, ucon | __SHIFTIN(3, UCON_RXTO)); 291 WR4(sc, SSCOM_UINTM, ~0u); 336 WR4(sc, SSCOM_UTXH, c & 0xff); 399 WR4(sc, SSCOM_UINTM, ~0u & ~(UINT_RXD|UINT_ERROR)); 404 WR4(sc, SSCOM_UCON, ucon); 429 WR4(sc, SSCOM_UINTM, ~0u); 434 WR4(s [all...] |
/netbsd-current/sys/arch/arm/xscale/ |
H A D | ixp425_if_npe.c | 186 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) function 352 WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 400 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 401 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 742 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 743 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 744 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 745 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 746 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 747 WR4(s [all...] |