Searched refs:WR0 (Results 1 - 9 of 9) sorted by relevance
| /netbsd-current/sys/arch/luna68k/stand/boot/ |
| H A D | sio.c | 116 sioreg(REG(unit, WR0), WR0_ERRRST);
216 sioreg(REG(0, WR0), WR0_CHANRST);
224 sioreg(REG(0, WR0), WR0_RSTINT);
232 sioreg(REG(0, WR0), WR0_RSTINT);
237 sioreg(REG(1, WR0), WR0_CHANRST);
240 sioreg(REG(1, WR0), WR0_RSTINT);
248 sioreg(REG(1, WR0), WR0_RSTINT);
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| H A D | sioreg.h | 92 #define WR0 0x00 macro
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| /netbsd-current/sys/arch/luna68k/dev/ |
| H A D | siovar.h | 76 if (regno != WR0)
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| H A D | sioreg.h | 73 #define WR0 0x00 macro
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| H A D | siotty.c | 189 setsioreg(sc->sc_ctl, WR0, WR0_CHANRST);
192 setsioreg(sc->sc_ctl, WR0, sc->sc_wr[WR0]);
196 setsioreg(sc->sc_ctl, WR0, sc->sc_wr[WR0]);
718 setsioreg(sio, WR0, WR0_CHANRST);
721 setsioreg(sio, WR0, ch0_regs[WR0]);
725 setsioreg(sio, WR0, ch0_regs[WR0]);
[all...] |
| H A D | lunaws.c | 232 setsioreg(sc->sc_ctl, WR0, sc->sc_wr[WR0]);
236 setsioreg(sc->sc_ctl, WR0, sc->sc_wr[WR0]);
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorPrint.cpp | 76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) ||
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 681 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
685 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
699 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
709 ? Producer - Hexagon::WR0
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 505 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
613 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
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