Searched refs:VISLANDS30_IV_SRCID_D1_V_UPDATE_INT (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/ivsrcid/
H A Divsrcid_vislands30.h32 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
H A Damdgpu_irq_service_dce110.c345 case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c2209 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {

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