Searched refs:UseReg (Results 1 - 8 of 8) sorted by relevance
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCPreEmitPeephole.cpp | 254 Register UseReg; member in struct:__anon2577::PPCPreEmitPeephole::GOTDefUsePair 298 Pair.UseReg = BBI->getOperand(0).getReg(); 316 if (BBI->readsRegister(Pair->UseReg, TRI) || 317 BBI->modifiesRegister(Pair->UseReg, TRI)) { 333 MachineOperand::CreateReg(Pair->UseReg, true, true); 335 MachineOperand::CreateReg(Pair->UseReg, false, true);
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H A D | PPCVSXSwapRemoval.cpp | 722 Register UseReg = MI->getOperand(0).getReg(); local 723 MachineInstr *DefMI = MRI->getVRegDef(UseReg); 799 Register UseReg = MI->getOperand(0).getReg(); local 800 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64StackTaggingPreRA.cpp | 280 Register UseReg = WorkList.back(); local 282 for (auto &UseI : MRI->use_instructions(UseReg)) { 297 << Register::virtReg2Index(UseReg) << " in " << UseI
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 248 /// Returns true if it is unsafe to move a copy instruction from \p UseReg to 250 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, argument 253 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || 259 static Register UseReg(const MachineOperand& MO) { function 270 Register I2UseReg = UseReg(I2.getOperand(1)); 337 Register I1UseReg = UseReg(I1.getOperand(1));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIFoldOperands.cpp | 493 // Find a def of the UseReg, check if it is a reg_sequence and find initializers 498 Register UseReg, uint8_t OpTy, 500 MachineInstr *Def = MRI.getVRegDef(UseReg); 555 Register UseReg = OpToFold.getReg(); 556 if (!UseReg.isVirtual()) 565 MachineInstr *Def = MRI.getVRegDef(UseReg); 577 if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI)) 743 Register UseReg = OpToFold.getReg(); local 744 UseMI->getOperand(1).setReg(UseReg); 756 getRegSeqInit(Defs, UseReg, AMDGP 496 getRegSeqInit( SmallVectorImpl<std::pair<MachineOperand*, unsigned>> &Defs, Register UseReg, uint8_t OpTy, const SIInstrInfo *TII, const MachineRegisterInfo &MRI) argument 916 Register UseReg = UseOp.getReg(); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCodeEmitter.cpp | 731 unsigned UseReg = MO.getReg(); 755 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { 774 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegStackify.cpp | 909 unsigned UseReg = SubsequentUse->getReg(); local 911 if (DefReg != UseReg || !MRI.hasOneUse(DefReg))
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 207 unsigned ARMSelectCallOp(bool UseReg); 2170 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { argument 2171 if (UseReg) 2383 bool UseReg = false; 2385 if (!GV || Subtarget->genLongCalls()) UseReg = true; 2388 if (UseReg) { 2398 unsigned CallOpc = ARMSelectCallOp(UseReg); 2405 if (UseReg) {
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