| /netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenInstruction.h | 33 enum { None, EarlyClobber, Tied } Kind = None; enumerator in enum:llvm::CGIOperandList::ConstraintInfo::__anon3276
48 I.Kind = Tied;
55 bool isTied() const { return Kind == Tied; }
65 if (Kind == Tied && OtherTiedOperand != RHS.OtherTiedOperand)
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 295 RI.Tied = true;
301 else if (!RI.Tied &&
303 RI.Tied = true;
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| H A D | InlineSpiller.cpp | 614 if (RI.Tied) {
865 // Tied use operands should not be passed to foldMemoryOperand.
883 unsigned Tied = MI->findTiedOperandIdx(Idx); local
885 TiedOps.emplace_back(Tied, Idx);
887 assert(MO.isDef() && "Tied to not use and def?");
888 TiedOps.emplace_back(Idx, Tied);
898 for (auto Tied : TiedOps)
899 MI->tieOperands(Tied.first, Tied.second);
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| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 226 /// Tied - Uses and defs must use the same register. This can be because of
229 bool Tied; member in struct:llvm::VirtRegInfo
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 616 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, local
618 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
620 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
624 MCOperand::createReg(MI.getOperand(Tied).getReg()),
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| /netbsd-current/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntime.h | 122 bool Tied = true; member in struct:clang::CodeGen::final
968 /// \param Tied true if task is generated for tied task, false otherwise.
976 bool Tied, unsigned &NumberOfParts);
1952 /// \param Tied true if task is generated for tied task, false otherwise.
1960 bool Tied, unsigned &NumberOfParts) override;
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| H A D | CGOpenMPRuntime.cpp | 153 UntiedTaskActionTy(bool Tied, const VarDecl *PartIDVar, argument
155 : Untied(!Tied), PartIDVar(PartIDVar), UntiedCodeGen(UntiedCodeGen) {}
1306 bool Tied, unsigned &NumberOfParts) {
1320 CGOpenMPTaskOutlinedRegionInfo::UntiedTaskActionTy Action(Tied, PartIDVar,
1344 if (!Tied)
4301 unsigned Flags = Data.Tied ? TiedFlag : 0;
5151 if (!Data.Tied) {
12605 bool Tied, unsigned &NumberOfParts) {
1302 emitTaskOutlinedFunction( const OMPExecutableDirective &D, const VarDecl *ThreadIDVar, const VarDecl *PartIDVar, const VarDecl *TaskTVar, OpenMPDirectiveKind InnermostKind, const RegionCodeGenTy &CodeGen, bool Tied, unsigned &NumberOfParts) argument
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| H A D | CGStmtOpenMP.cpp | 4335 if (!Data.Tied) {
4545 S, *I, *PartId, *TaskT, S.getDirectiveKind(), CodeGen, Data.Tied,
4710 S, *I, *PartId, *TaskT, S.getDirectiveKind(), CodeGen, /*Tied=*/true,
4737 Data.Tied = !S.getSingleClause<OMPUntiedClause>();
6847 Data.Tied = true;
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 1124 auto Tied = MI.getOperand(TiedIdx); local
1126 SDWAInst.add(Tied);
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| H A D | AMDGPUInstructionSelector.cpp | 1700 Register Tied = MRI->cloneVirtualRegister(VDataOut); local
1704 auto Parts = TRI.getRegSplitParts(MRI->getRegClass(Tied), 4);
1709 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), Tied);
1718 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), Tied);
1723 MIB.addReg(Tied, RegState::Implicit);
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