/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRMCAsmInfo.cpp | 19 AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { argument
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H A D | AVRMCAsmInfo.h | 25 explicit AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCSubtarget.cpp | 27 ARCSubtarget::ARCSubtarget(const Triple &TT, const std::string &CPU, argument 29 : ARCGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), FrameLowering(*this),
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreSubtarget.cpp | 27 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU, argument 29 : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 95 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { argument 96 if (TT.isOSBinFormatMachO()) { 97 if (TT.getArch() == Triple::x86_64) 102 if (TT.isOSBinFormatCOFF()) 107 static std::string computeDataLayout(const Triple &TT) { argument 111 Ret += DataLayout::getManglingComponent(TT); 113 if ((TT.isArch64Bit() && 114 (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) || 115 !TT 155 getEffectiveRelocModel(const Triple &TT, bool JIT, Optional<Reloc::Model> RM) argument 211 X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument 438 const Triple &TT = TM->getTargetTriple(); local 491 const Triple &TT = TM->getTargetTriple(); local 555 const Triple &TT = TM->getTargetTriple(); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySubtarget.cpp | 40 WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT, argument 44 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), 45 TargetTriple(TT), FrameLowering(),
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCAsmInfo.h | 25 explicit XCoreMCAsmInfo(const Triple &TT);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/MCTargetDesc/ |
H A D | ARCMCAsmInfo.h | 26 explicit ARCMCAsmInfo(const Triple &TT);
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H A D | ARCMCTargetDesc.cpp | 43 static MCRegisterInfo *createARCMCRegisterInfo(const Triple &TT) { argument 49 static MCSubtargetInfo *createARCMCSubtargetInfo(const Triple &TT, argument 51 return createARCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS); 55 const Triple &TT, 57 MCAsmInfo *MAI = new ARCMCAsmInfo(TT); 54 createARCMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCAsmInfo.h | 25 explicit HexagonMCAsmInfo(const Triple &TT);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCAsmInfo.h | 25 explicit MSP430MCAsmInfo(const Triple &TT, const MCTargetOptions &Options);
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H A D | MSP430MCAsmInfo.cpp | 18 MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT, argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCAsmInfo.h | 21 explicit SystemZMCAsmInfo(const Triple &TT);
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H A D | SystemZMCAsmInfo.cpp | 15 SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) { argument 20 AssemblerDialect = TT.isOSzOS() ? AD_HLASM : AD_ATT;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFMCAsmInfo.h | 23 explicit BPFMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { argument 24 if (TT.getArch() == Triple::bpfeb)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
H A D | M68kMCTargetDesc.cpp | 43 static std::string ParseM68kTriple(const Triple &TT, StringRef CPU) { argument 53 static MCRegisterInfo *createM68kMCRegisterInfo(const Triple &TT) { argument 59 static MCSubtargetInfo *createM68kMCSubtargetInfo(const Triple &TT, argument 61 std::string ArchFS = ParseM68kTriple(TT, CPU); 69 return createM68kMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, ArchFS); 73 const Triple &TT, 75 MCAsmInfo *MAI = new M68kELFMCAsmInfo(TT); 72 createM68kMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &TO) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ |
H A D | TargetMachine.cpp | 35 const Triple &TT, StringRef CPU, StringRef FS, 37 : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), 96 const Triple &TT = getTargetTriple(); local 112 return TT.isOSBinFormatCOFF(); 127 if (TT.isWindowsGNUEnvironment() && TT.isOSBinFormatCOFF() && 134 if (TT.isOSBinFormatCOFF() && GV->hasExternalWeakLinkage()) 143 if (TT.isOSBinFormatCOFF() || TT.isOSWindows()) 146 if (TT 34 TargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430TargetMachine.cpp | 35 static std::string computeDataLayout(const Triple &TT, StringRef CPU, argument 40 MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, argument 46 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, 50 Subtarget(TT, std::string(CPU), std::string(FS), *this) {
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/CSKY/MCTargetDesc/ |
H A D | CSKYMCTargetDesc.cpp | 36 const Triple &TT, 38 MCAsmInfo *MAI = new CSKYMCAsmInfo(TT); 61 static MCRegisterInfo *createCSKYMCRegisterInfo(const Triple &TT) { argument 67 static MCSubtargetInfo *createCSKYMCSubtargetInfo(const Triple &TT, argument 72 return createCSKYMCSubtargetInfoImpl(TT, CPUName, /*TuneCPU=*/CPUName, FS); 35 createCSKYMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackendDarwin.h | 19 Triple TT; member in class:llvm::ARMAsmBackendDarwin 25 TT(STI.getTargetTriple()), 32 /*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCAsmInfo.cpp | 17 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT, argument 20 CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4; 28 MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16;
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H A D | AMDGPUMCAsmInfo.h | 28 explicit AMDGPUMCAsmInfo(const Triple &TT, const MCTargetOptions &Options);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VESubtarget.cpp | 44 VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU, argument 46 : VEGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT),
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCAsmBackend.cpp | 84 Triple TT; member in class:__anon2552::PPCAsmBackend 86 PPCAsmBackend(const Target &T, const Triple &TT) argument 87 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), 88 TT(TT) {} 217 ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {} argument 221 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 222 bool Is64 = TT.isPPC64(); 231 XCOFFPPCAsmBackend(const Target &T, const Triple &TT) argument 275 const Triple &TT = STI.getTargetTriple(); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 36 const Triple &TT, 38 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 46 const Triple &TT, 48 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 61 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) { argument 68 createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument 70 CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; 71 return createSparcMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 35 createSparcMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument 45 createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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