/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 1272 SDValue SubVec = N->getOperand(1); local 1279 EVT SubVecVT = SubVec.getValueType(); 1289 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); 1297 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, 1317 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, 2380 assert(OpNo == 1 && "Invalid OpNo; can only split SubVec."); 2385 SDValue SubVec = N->getOperand(1); local 2390 GetSplitVector(SubVec, Lo, Hi); 4843 SDValue SubVec = N->getOperand(1); local 4849 if (getTypeAction(SubVec [all...] |
H A D | SelectionDAGBuilder.cpp | 7116 SDValue SubVec = getValue(I.getOperand(1)); local 7127 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec,
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H A D | DAGCombiner.cpp | 18236 SDValue SubVec = InsertVal.getOperand(0); 18238 EVT SubVecVT = SubVec.getValueType(); 18271 ConcatOps[0] = SubVec;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 6155 SDValue SubVec = Op.getOperand(1); 6160 if (SubVec.isUndef()) 6181 SubVec, Idx); 6185 MVT SubVecVT = SubVec.getSimpleValueType(); 6200 // Merge them together, SubVec should be zero extended. 6201 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, 6203 SubVec, ZeroIdx); 6204 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); 6208 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, 6209 Undef, SubVec, ZeroId [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCalls.cpp | 1852 Value *SubVec = II->getArgOperand(1); local 1856 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); 1858 // Only canonicalize if the destination vector, Vec, and SubVec are all 1867 // of the SubVec's minimum vector length OR the insertion overruns Vec. 1873 // An insert that entirely overwrites Vec with SubVec is a nop. 1875 replaceInstUsesWith(CI, SubVec); 1879 // Widen SubVec into a vector of the same width as Vec, since 1881 // Elements beyond the bounds of SubVec within the widened vector are 1890 Value *WidenShuffle = Builder.CreateShuffleVector(SubVec, WidenMask);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 3668 SDValue SubVec = Op.getOperand(1); local 3670 MVT SubVecVT = SubVec.getSimpleValueType(); 3697 SubVec = DAG.getBitcast(SubVecVT, SubVec); 3706 SubVec = DAG.getNode(ISD::ZERO_EXTEND, DL, ExtSubVecVT, SubVec); 3707 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, 3727 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, 3728 DAG.getUNDEF(ContainerVT), SubVec, 3738 SubVec, SlideupAm [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | IRBuilder.h | 909 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec, argument 912 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 8739 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); local 8743 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, 8749 return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec, 15207 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, local 15210 DAG.getStore(St->getChain(), DL, SubVec, BasePtr, St->getPointerInfo(), 19733 Value *SubVec = Builder.CreateExtractValue(VldN, Index); local 19737 SubVec = Builder.CreateIntToPtr( 19738 SubVec, 19741 SubVecs[SV].push_back(SubVec); 19750 auto &SubVec = SubVecs[SVI]; local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 11404 Value *SubVec = Builder.CreateExtractValue(LdN, Index); local 11408 SubVec = Builder.CreateIntToPtr( 11409 SubVec, FixedVectorType::get(SVI->getType()->getElementType(), 11411 SubVecs[SVI].push_back(SubVec); 11420 auto &SubVec = SubVecs[SVI]; local 11422 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0];
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 5738 Value *SubVec = Call->getArgOperand(1); local 5746 if (match(SubVec, m_Intrinsic<Intrinsic::experimental_vector_extract>(
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 5540 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, 5543 Pieces.push_back(SubVec);
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