Searched refs:SrcHi (Results 1 - 6 of 6) sorted by relevance
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRInstrInfo.cpp | 55 Register DestLo, DestHi, SrcLo, SrcHi; local 58 TRI.splitReg(SrcReg, SrcLo, SrcHi); 64 .addReg(SrcHi, getKillRegState(KillSrc));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 739 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); local 754 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); local 882 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi)); 884 .addReg(SrcHi, KillFlag | UndefHi) 1055 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); local 1058 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); 1061 .addReg(SrcHi, UndefHi) 1325 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); local 1329 .addReg(SrcHi) 1337 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); local 1341 .addReg(SrcHi) [all...] |
H A D | HexagonFrameLowering.cpp | 1933 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); local 1959 if (LPR.contains(SrcHi)) { 1965 .addReg(SrcHi, getKillRegState(IsKill))
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 2117 SDValue SrcLo, SrcHi; local 2120 GetSplitVector(N->getOperand(0), SrcLo, SrcHi); 2122 std::tie(SrcLo, SrcHi) = DAG.SplitVectorOperand(N, 0); 2125 Hi = DAG.getNode(N->getOpcode(), dl, DstVTHi, SrcHi, N->getOperand(1));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 6699 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, local 6701 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ);
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