Searched refs:SchedReads (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenSchedule.h111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
431 std::vector<CodeGenSchedRW> SchedReads; member in class:llvm::CodeGenSchedModels
517 assert(Idx < SchedReads.size() && "bad SchedRead index");
518 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
519 return SchedReads[Idx];
H A DCodeGenSchedule.cpp185 // defined, and populate SchedReads and SchedWrites vectors. Implicit
590 SchedReads.resize(1);
667 SchedReads.emplace_back(SchedReads.size(), SRDef);
692 } for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd;
695 SchedReads[RIdx].dump();
722 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
729 for (const CodeGenSchedRW &Read : SchedReads) {
832 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
852 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads
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