Searched refs:SIM_CPU (Results 1 - 25 of 357) sorted by relevance

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/netbsd-current/external/gpl3/gdb.old/dist/sim/frv/
H A Dprofile-fr500.h23 void fr500_model_insn_before (SIM_CPU *, int);
24 void fr500_model_insn_after (SIM_CPU *, int, int);
26 void fr500_reset_fr_flags (SIM_CPU *, INT);
27 void fr500_reset_cc_flags (SIM_CPU *, INT);
H A Dprofile-fr550.h23 void fr550_model_insn_before (SIM_CPU *, int);
24 void fr550_model_insn_after (SIM_CPU *, int, int);
H A Dprofile-fr400.h23 void fr400_model_insn_before (SIM_CPU *, int);
24 void fr400_model_insn_after (SIM_CPU *, int, int);
26 void fr400_reset_gr_flags (SIM_CPU *, INT);
27 void fr400_reset_fr_flags (SIM_CPU *, INT);
28 void fr400_reset_acc_flags (SIM_CPU *, INT);
H A Dprofile.h108 void update_GR_latency (SIM_CPU *, INT, int);
109 void update_GRdouble_latency (SIM_CPU *, INT, int);
110 void update_GR_latency_for_load (SIM_CPU *, INT, int);
111 void update_GRdouble_latency_for_load (SIM_CPU *, INT, int);
112 void update_GR_latency_for_swap (SIM_CPU *, INT, int);
113 void update_FR_latency (SIM_CPU *, INT, int);
114 void update_FRdouble_latency (SIM_CPU *, INT, int);
115 void update_FR_latency_for_load (SIM_CPU *, INT, int);
116 void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
117 void update_FR_ptime (SIM_CPU *, IN
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H A Dregisters.h46 void frv_register_control_init (SIM_CPU *);
47 void frv_initialize_spr (SIM_CPU *);
48 void frv_reset_spr (SIM_CPU *);
50 void frv_check_spr_access (SIM_CPU *, UINT);
52 void frv_fr_registers_available (SIM_CPU *, int *, int *);
53 void frv_gr_registers_available (SIM_CPU *, int *, int *);
54 int frv_check_register_access (SIM_CPU *, SI, int, int);
55 int frv_check_gr_access (SIM_CPU *, SI);
56 int frv_check_fr_access (SIM_CPU *, SI);
/netbsd-current/external/gpl3/gdb/dist/sim/frv/
H A Dprofile-fr500.h23 void fr500_model_insn_before (SIM_CPU *, int);
24 void fr500_model_insn_after (SIM_CPU *, int, int);
26 void fr500_reset_fr_flags (SIM_CPU *, INT);
27 void fr500_reset_cc_flags (SIM_CPU *, INT);
H A Dprofile-fr550.h23 void fr550_model_insn_before (SIM_CPU *, int);
24 void fr550_model_insn_after (SIM_CPU *, int, int);
H A Dprofile-fr400.h23 void fr400_model_insn_before (SIM_CPU *, int);
24 void fr400_model_insn_after (SIM_CPU *, int, int);
26 void fr400_reset_gr_flags (SIM_CPU *, INT);
27 void fr400_reset_fr_flags (SIM_CPU *, INT);
28 void fr400_reset_acc_flags (SIM_CPU *, INT);
H A Dprofile.h108 void update_GR_latency (SIM_CPU *, INT, int);
109 void update_GRdouble_latency (SIM_CPU *, INT, int);
110 void update_GR_latency_for_load (SIM_CPU *, INT, int);
111 void update_GRdouble_latency_for_load (SIM_CPU *, INT, int);
112 void update_GR_latency_for_swap (SIM_CPU *, INT, int);
113 void update_FR_latency (SIM_CPU *, INT, int);
114 void update_FRdouble_latency (SIM_CPU *, INT, int);
115 void update_FR_latency_for_load (SIM_CPU *, INT, int);
116 void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
117 void update_FR_ptime (SIM_CPU *, IN
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H A Dregisters.h46 void frv_register_control_init (SIM_CPU *);
47 void frv_initialize_spr (SIM_CPU *);
48 void frv_reset_spr (SIM_CPU *);
50 void frv_check_spr_access (SIM_CPU *, UINT);
51 void frv_check_spr_read_access (SIM_CPU *, UINT);
52 void frv_check_spr_write_access (SIM_CPU *, UINT);
54 void frv_fr_registers_available (SIM_CPU *, int *, int *);
55 void frv_gr_registers_available (SIM_CPU *, int *, int *);
56 int frv_check_register_access (SIM_CPU *, SI, int, int);
57 int frv_check_gr_access (SIM_CPU *, S
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/netbsd-current/external/gpl3/gdb.old/dist/sim/bfin/
H A Ddv-bfin_evt.h24 extern void cec_set_evt (SIM_CPU *, int ivg, bu32 handler_addr);
25 extern bu32 cec_get_evt (SIM_CPU *, int ivg);
26 extern bu32 cec_get_reset_evt (SIM_CPU *);
/netbsd-current/external/gpl3/gdb/dist/sim/bfin/
H A Ddv-bfin_evt.h24 extern void cec_set_evt (SIM_CPU *, int ivg, bu32 handler_addr);
25 extern bu32 cec_get_evt (SIM_CPU *, int ivg);
26 extern bu32 cec_get_reset_evt (SIM_CPU *);
/netbsd-current/external/gpl3/gdb.old/dist/sim/sh64/
H A Ddecode-compact.h27 extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
30 extern void sh64_compact_init_idesc_table (SIM_CPU *);
31 extern void sh64_compact_sem_init_idesc_table (SIM_CPU *);
32 extern void sh64_compact_semf_init_idesc_table (SIM_CPU *);
130 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
131 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
132 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
133 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
134 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
135 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, cons
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H A Ddecode-media.h27 extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
30 extern void sh64_media_init_idesc_table (SIM_CPU *);
31 extern void sh64_media_sem_init_idesc_table (SIM_CPU *);
32 extern void sh64_media_semf_init_idesc_table (SIM_CPU *);
120 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
121 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
122 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
123 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
124 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
125 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, cons
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H A Deng-compact.h30 extern SEM_PC sh64_compact_pbb_begin (SIM_CPU *, int);
31 extern SEM_PC sh64_compact_pbb_chain (SIM_CPU *, SEM_ARG);
32 extern SEM_PC sh64_compact_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
33 extern void sh64_compact_pbb_before (SIM_CPU *, SCACHE *);
34 extern void sh64_compact_pbb_after (SIM_CPU *, SCACHE *);
H A Deng-media.h30 extern SEM_PC sh64_media_pbb_begin (SIM_CPU *, int);
31 extern SEM_PC sh64_media_pbb_chain (SIM_CPU *, SEM_ARG);
32 extern SEM_PC sh64_media_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
33 extern void sh64_media_pbb_before (SIM_CPU *, SCACHE *);
34 extern void sh64_media_pbb_after (SIM_CPU *, SCACHE *);
H A Dsh64-sim.h32 BI sh64_endian (SIM_CPU *);
33 VOID sh64_break (SIM_CPU *, PCADDR);
34 SI sh64_movua (SIM_CPU *, PCADDR, SI);
35 VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
36 VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);
38 SF sh64_fldi0 (SIM_CPU *);
39 SF sh64_fldi1 (SIM_CPU *);
40 DF sh64_fcnvsd (SIM_CPU *, SF);
41 SF sh64_fcnvds (SIM_CPU *, DF);
43 DF sh64_fabsd (SIM_CPU *, D
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H A Dcpu.c33 sh64_h_pc_get (SIM_CPU *current_cpu)
41 sh64_h_pc_set (SIM_CPU *current_cpu, UDI newval)
49 sh64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
57 sh64_h_gr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
65 sh64_h_grc_get (SIM_CPU *current_cpu, UINT regno)
73 sh64_h_grc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
81 sh64_h_cr_get (SIM_CPU *current_cpu, UINT regno)
89 sh64_h_cr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
97 sh64_h_sr_get (SIM_CPU *current_cpu)
105 sh64_h_sr_set (SIM_CPU *current_cp
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/netbsd-current/external/gpl3/gdb.old/dist/sim/or1k/
H A Dcpu.c34 or1k32bf_h_pc_get (SIM_CPU *current_cpu)
42 or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
50 or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
58 or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
66 or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
74 or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
82 or1k32bf_h_fsr_get (SIM_CPU *current_cpu, UINT regno)
90 or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
98 or1k32bf_h_fd32r_get (SIM_CPU *current_cpu, UINT regno)
106 or1k32bf_h_fd32r_set (SIM_CPU *current_cp
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/netbsd-current/external/gpl3/gdb/dist/sim/or1k/
H A Dcpu.c34 or1k32bf_h_pc_get (SIM_CPU *current_cpu)
42 or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
50 or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
58 or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
66 or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
74 or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
82 or1k32bf_h_fsr_get (SIM_CPU *current_cpu, UINT regno)
90 or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
98 or1k32bf_h_fd32r_get (SIM_CPU *current_cpu, UINT regno)
106 or1k32bf_h_fd32r_set (SIM_CPU *current_cp
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/netbsd-current/external/gpl3/gdb.old/dist/sim/cris/
H A Dcpuv32.c33 crisv32f_h_v32_v32_get (SIM_CPU *current_cpu)
41 crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval)
49 crisv32f_h_pc_get (SIM_CPU *current_cpu)
57 crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval)
65 crisv32f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
73 crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
81 crisv32f_h_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
89 crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
97 crisv32f_h_raw_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
105 crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cp
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/netbsd-current/external/gpl3/gdb/dist/sim/cris/
H A Dcpuv32.c33 crisv32f_h_v32_v32_get (SIM_CPU *current_cpu)
41 crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval)
49 crisv32f_h_pc_get (SIM_CPU *current_cpu)
57 crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval)
65 crisv32f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
73 crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
81 crisv32f_h_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
89 crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
97 crisv32f_h_raw_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
105 crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cp
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/netbsd-current/external/gpl3/gdb.old/dist/sim/m32r/
H A Dcpux.c33 m32rxf_h_pc_get (SIM_CPU *current_cpu)
41 m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
49 m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
57 m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
65 m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
73 m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
81 m32rxf_h_accum_get (SIM_CPU *current_cpu)
89 m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
97 m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
105 m32rxf_h_accums_set (SIM_CPU *current_cp
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H A Dcpu2.c33 m32r2f_h_pc_get (SIM_CPU *current_cpu)
41 m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)
49 m32r2f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
57 m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
65 m32r2f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
73 m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
81 m32r2f_h_accum_get (SIM_CPU *current_cpu)
89 m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)
97 m32r2f_h_accums_get (SIM_CPU *current_cpu, UINT regno)
105 m32r2f_h_accums_set (SIM_CPU *current_cp
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/netbsd-current/external/gpl3/gdb.old/dist/sim/iq2000/
H A Dcpu.c33 iq2000bf_h_pc_get (SIM_CPU *current_cpu)
41 iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
49 iq2000bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
57 iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
65 iq2000bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,

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