/netbsd-current/sys/arch/aarch64/aarch64/ |
H A D | disasm.c | 889 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, 902 ZREGNAME(0, Rt), 910 ZREGNAME(0, Rt), 921 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, 934 ZREGNAME(RtSz, Rt), 940 ZREGNAME(RtSz, Rt), 948 ZREGNAME(RtSz, Rt), 959 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, 972 ZREGNAME(1, Rt), 978 ZREGNAME(1, Rt), 888 regoffset_b_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn, uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, const char *op) argument 920 regoffset_h_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn, uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, uint64_t RtSz, const char *op) argument 958 regoffset_w_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn, uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, const char *op) argument 996 regoffset_x_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn, uint64_t size, uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, const char *op) argument [all...] |
/netbsd-current/sys/external/bsd/compiler_rt/dist/lib/xray/ |
H A D | xray_mips.cc | 42 uint32_t Rt, 44 return (Opcode | Rs << 21 | Rt << 16 | Imm); 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, 50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
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H A D | xray_mips64.cc | 43 uint32_t Rt, 45 return (Opcode | Rs << 21 | Rt << 16 | Imm); 49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, 51 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 680 if (Rs >= Rt) { 683 } else if (Rs != 0 && Rs < Rt) { 694 Rt))); 704 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 708 if (Rs >= Rt) { 711 Rt))); 715 } else if (Rs != 0 && Rs < Rt) { 720 Rt))); 725 Rt))); 749 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 777 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 818 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 857 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 901 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 946 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 988 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 1093 InsnType Rt = fieldFromInstruction(Insn, 16, 5); local 1135 InsnType Rt = fieldFromInstruction(Insn, 16, 5); local 1153 InsnType Rt = fieldFromInstruction(Insn, 16, 5); local 2050 unsigned Rt = fieldFromInstruction(Insn, 16, 5); local 2560 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 2609 InsnType Rt = fieldFromInstruction(insn, 21, 5); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; local 211 Rt = L.getOperand(0); 216 CompoundInsn->addOperand(Rt); 222 Rt = L.getOperand(0); 228 CompoundInsn->addOperand(Rt); 237 Rt = L.getOperand(2); 243 CompoundInsn->addOperand(Rt); 250 Rt = L.getOperand(2); 256 CompoundInsn->addOperand(Rt); 263 Rt [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 370 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo 374 MCOperand &Rt = Inst.getOperand(3); local 375 assert(Rt.isReg() && "Expected register and none was found"); 376 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); 385 MCOperand &Rt = Inst.getOperand(2); local 386 assert(Rt.isReg() && "Expected register and none was found"); 387 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 392 Rt 397 MCOperand &Rt = Inst.getOperand(2); local 594 MCOperand &Rt = Inst.getOperand(1); local [all...] |
H A D | HexagonBitTracker.cpp | 294 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt, 297 assert(Ws == Rt.width()); 298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); 301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
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H A D | HexagonBitSimplify.cpp | 582 case S2_storerf_io: // memh(Rs32+#s11:1)=Rt.H32 583 case S2_pstorerft_io: // if (Pv4) memh(Rs32+#u6:1)=Rt.H32 584 case S2_pstorerff_io: // if (!Pv4) memh(Rs32+#u6:1)=Rt.H32 585 case S4_pstorerftnew_io: // if (Pv4.new) memh(Rs32+#u6:1)=Rt.H32 586 case S4_pstorerffnew_io: // if (!Pv4.new) memh(Rs32+#u6:1)=Rt.H32 587 case S2_storerf_pi: // memh(Rx32++#s4:1)=Rt.H32 588 case S2_pstorerft_pi: // if (Pv4) memh(Rx32++#s4:1)=Rt.H32 589 case S2_pstorerff_pi: // if (!Pv4) memh(Rx32++#s4:1)=Rt.H32 590 case S2_pstorerftnew_pi: // if (Pv4.new) memh(Rx32++#s4:1)=Rt.H32 591 case S2_pstorerffnew_pi: // if (!Pv4.new) memh(Rx32++#s4:1)=Rt [all...] |
H A D | HexagonSplitDouble.cpp | 375 Register Rt = MI->getOperand(2).getReg(); local 376 return profit(Rs) + profit(Rt);
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/netbsd-current/external/gpl3/gdb.old/dist/sim/arm/ |
H A D | thumbemu.c | 318 ARMword Rt = ntBITS (12, 15); local 325 tASSERT (Rt2 == Rt + 1); 345 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}] 346 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8> 347 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]! 356 * ainstr |= (Rt << 12); 1126 ARMword Rt = ntBITS (12, 15); local 1132 tASSERT (Rt != 15); 1134 /* LDRB<c> <Rt>,<label> => 1111 1000 U001 1111 */ 1141 /* LDRB<c>.W <Rt>,[<R 1221 ARMword Rt = ntBITS (12, 15); local 1317 ARMword Rt = ntBITS (12, 15); local 1419 ARMword Rt = ntBITS (12, 15); local 1443 ARMword Rt = ntBITS (12, 15); local 1501 ARMword Rt = ntBITS (12, 15); local [all...] |
/netbsd-current/external/gpl3/gdb/dist/sim/arm/ |
H A D | thumbemu.c | 321 ARMword Rt = ntBITS (12, 15); local 328 tASSERT (Rt2 == Rt + 1); 348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}] 349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8> 350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]! 359 * ainstr |= (Rt << 12); 1129 ARMword Rt = ntBITS (12, 15); local 1135 tASSERT (Rt != 15); 1137 /* LDRB<c> <Rt>,<label> => 1111 1000 U001 1111 */ 1144 /* LDRB<c>.W <Rt>,[<R 1224 ARMword Rt = ntBITS (12, 15); local 1320 ARMword Rt = ntBITS (12, 15); local 1422 ARMword Rt = ntBITS (12, 15); local 1446 ARMword Rt = ntBITS (12, 15); local 1504 ARMword Rt = ntBITS (12, 15); local [all...] |
/netbsd-current/external/gpl3/binutils/dist/opcodes/ |
H A D | aarch64-tbl.h | 3430 CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3431 CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3669 CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3670 CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3671 CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), 3674 CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3675 CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3676 CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), 3677 CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 3678 CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/ |
H A D | aarch64-tbl.h | 3254 CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3255 CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3493 CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3494 CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3495 CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), 3498 CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3499 CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3500 CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), 3501 CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 3502 CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM [all...] |
/netbsd-current/external/gpl3/gdb/dist/opcodes/ |
H A D | aarch64-tbl.h | 3444 CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3445 CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3683 CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3684 CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3685 CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), 3688 CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3689 CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3690 CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), 3691 CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 3692 CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM [all...] |
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/ |
H A D | aarch64-tbl.h | 3430 CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3431 CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 3669 CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3670 CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 3671 CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), 3674 CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3675 CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 3676 CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), 3677 CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 3678 CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1075 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1085 // Rt is an immediate in prefetch. 1086 Inst.addOperand(MCOperand::createImm(Rt)); 1096 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1103 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1107 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1111 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1115 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1119 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1123 DecodeFPR8RegisterClass(Inst, Rt, Add 1136 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1334 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1417 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1551 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1830 uint64_t Rt = fieldFromInstruction(insn, 0, 5); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 1857 // On stores, the writeback operand precedes Rt. 1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1877 // On loads, the writeback operand comes after Rt. 1908 if (writeback && (Rn == 15 || Rn == Rt)) 1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 2006 unsigned Rt2 = Rt + 1; 2010 // For {LD,ST}RD, Rt must be even, else undefined. 2018 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2030 if (writeback && (Rn == 15 || Rn == Rt || R 3792 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3960 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4040 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4078 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4315 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4778 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4801 unsigned Rt = fieldFromInstruction(Insn, 0, 4); local 4826 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4878 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4903 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5474 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5500 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5557 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5594 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5663 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5844 unsigned Rt = fieldFromInstruction(Val, 12, 4); local 5873 unsigned Rt = fieldFromInstruction(Val, 12, 4); local 5930 unsigned Rt = fieldFromInstruction(Val, 12, 4); local 6456 unsigned Rt = fieldFromInstruction(Insn, 0, 4); local 6479 unsigned Rt = fieldFromInstruction(Insn, 0, 4); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg(); local 140 Register Reg = Rs == GAReg ? Rt : Rs;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1391 MCOperand &Rt = Inst.getOperand(1); local 1394 TmpInst.addOperand(Rt); 1395 TmpInst.addOperand(Rt); 1407 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" 1812 MCOperand &Rt = Inst.getOperand(2); local 1813 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 1818 Rt.setReg(matchRegister(RegPair)); 1823 Rt.setReg(matchRegister(RegPair)); 1832 MCOperand &Rt = Inst.getOperand(3); local 1833 unsigned int RegNum = RI->getEncodingValue(Rt 1855 MCOperand &Rt = Inst.getOperand(2); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); local 472 assert(isARMLowRegister(Rt)); 485 .addReg(Rt, IsStore ? 0 : RegState::Define);
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H A D | ARMBaseInstrInfo.cpp | 3472 Register Rt = MI.getOperand(0).getReg(); local 3474 return (Rt == Rm) ? 4 : 3; 3479 Register Rt = MI.getOperand(0).getReg(); local 3481 if (Rt == Rm) 3509 Register Rt = MI.getOperand(0).getReg(); local 3513 if (Rt == Rm) 3521 Register Rt = MI.getOperand(0).getReg(); local 3523 return (Rt == Rm) ? 3 : 2; 3544 Register Rt = MI.getOperand(0).getReg(); 3545 if (Rt 3559 Register Rt = MI.getOperand(0).getReg(); local 3585 Register Rt = MI.getOperand(0).getReg(); local 3595 Register Rt = MI.getOperand(0).getReg(); local 3632 Register Rt = MI.getOperand(0).getReg(); local [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/arm/ |
H A D | sp-pc-validations-bad-t.s | 53 @ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT 136 @ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 4200 // the Rt == Rt2. All of those are undefined behaviour. 4207 unsigned Rt = Inst.getOperand(1).getReg(); local 4210 if (RI->isSubRegisterEq(Rn, Rt)) 4224 unsigned Rt = Inst.getOperand(0).getReg(); local 4226 if (Rt == Rt2) 4227 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); 4237 unsigned Rt = Inst.getOperand(1).getReg(); local 4239 if (Rt == Rt2) 4240 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); 4253 unsigned Rt local 4286 unsigned Rt = Inst.getOperand(1).getReg(); local 4305 unsigned Rt = Inst.getOperand(1).getReg(); local 4321 unsigned Rt = Inst.getOperand(1).getReg(); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3515 Register Rt = MI.getOperand(1).getReg(); local 3540 .addReg(Rt) 3580 Register Rt = RegInfo.createVirtualRegister(RC); local 3583 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt); 3589 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32); 3590 Rt = Tmp; 3593 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5813 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2 5816 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt 7415 unsigned Rt = MRI->getEncodingValue(Reg1); local 7418 // Rt2 must be Rt + 1 and Rt must be even. 7419 if (Rt + 1 != Rt2 || (Rt & 1)) { 7536 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); local 7540 // Rt can't be R14. 7541 if (Rt 7761 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local 7774 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local 7821 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local [all...] |