Searched refs:RegNum (Results 1 - 25 of 45) sorted by relevance

12

/netbsd-current/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCRegisterInfo.cpp68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
74 DwarfLLVMRegPair Key = { RegNum, 0 };
76 if (I == M+Size || I->FromReg != RegNum)
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
88 DwarfLLVMRegPair Key = { RegNum, 0 };
90 if (I != M + Size && I->FromReg == RegNum)
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true))
106 return RegNum;
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) cons
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/netbsd-current/sys/external/bsd/compiler_rt/dist/lib/xray/
H A Dxray_mips.cc34 enum RegNum : uint32_t {
105 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
107 PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
109 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr);
111 PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr);
113 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID);
115 PatchOpcodes::PO_JALR, RegNum
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H A Dxray_mips64.cc35 enum RegNum : uint32_t {
105 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_RA, 0x8);
107 PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_T9, 0x0);
109 PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HighestTracingHookAddr);
111 encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9,
114 PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
46 // allocated yet. RegNum is actually an index into ArgRegs, which means we
47 // need to skip a register if RegNum is odd.
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
49 State.AllocateReg(ArgRegs[RegNum]);
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
68 int RegsLeft = NumArgRegs - RegNum;
72 if (RegNum != NumArgRegs && RegsLeft < 4) {
74 State.AllocateReg(ArgRegs[RegNum
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugFrame.cpp33 unsigned RegNum) {
35 if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(RegNum, IsEH)) {
42 OS << "reg" << RegNum; local
63 UnwindLocation UnwindLocation::createIsRegisterPlusOffset(uint32_t RegNum, argument
65 return {RegPlusOffset, RegNum, Offset, false};
67 UnwindLocation UnwindLocation::createAtRegisterPlusOffset(uint32_t RegNum, argument
69 return {RegPlusOffset, RegNum, Offset, true};
103 printRegister(OS, MRI, IsEH, RegNum);
138 return RegNum == RHS.RegNum
32 printRegister(raw_ostream &OS, const MCRegisterInfo *MRI, bool IsEH, unsigned RegNum) argument
356 uint64_t RegNum = Data.getULEB128(C); local
566 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
646 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
655 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
667 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
680 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
692 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
701 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
710 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
738 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.h47 int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo);
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
98 return getRegisterName(RegNum);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp206 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, argument
208 return std::make_unique<AVROperand>(RegNum, S, E);
217 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { argument
218 return std::make_unique<AVROperand>(RegNum, Val, S, E);
338 int RegNum = matchFn(Name); local
344 if (RegNum == AVR::NoRegister) {
345 RegNum = matchFn(Name.lower());
347 if (RegNum == AVR::NoRegister) {
348 RegNum = matchFn(Name.upper());
351 return RegNum;
355 int RegNum = parseRegisterName(&MatchRegisterName); local
364 int RegNum = AVR::NoRegister; local
722 int64_t RegNum = Const->getValue(); local
724 RegName << "r" << RegNum; local
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/
H A DDWARFDebugFrame.h65 uint32_t RegNum; /// The register number for Kind == RegPlusOffset. member in class:llvm::dwarf::UnwindLocation
75 : Kind(K), RegNum(InvalidRegisterNumber), Offset(0), Dereference(false) {}
78 : Kind(K), RegNum(Reg), Offset(Off), Dereference(Deref) {}
81 : Kind(DWARFExpr), RegNum(InvalidRegisterNumber), Offset(0), Expr(E),
120 uint32_t getRegister() const { return RegNum; }
126 void setRegister(uint32_t NewRegNum) { RegNum = NewRegNum; }
168 /// Return the location for the register in \a RegNum if there is a location.
170 /// \param RegNum the register number to find a location for.
172 /// \returns A location if one is available for \a RegNum, or llvm::None
174 Optional<UnwindLocation> getRegisterLocation(uint32_t RegNum) cons
186 setRegisterLocation(uint32_t RegNum, const UnwindLocation &Location) argument
194 removeRegisterLocation(uint32_t RegNum) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp207 unsigned RegNum; member in struct:__anon2383::HexagonOperand::RegTy
254 return Reg.RegNum;
433 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { argument
435 Op->Reg.RegNum = RegNum;
1779 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); local
1780 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1782 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1787 std::string Name = r + utostr(RegNum
1796 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); local
1813 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
1833 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
1856 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp198 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, argument
200 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E);
208 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, argument
211 return std::make_unique<MSP430Operand>(RegNum, Val, S, E);
214 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, argument
216 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E);
219 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, argument
221 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp69 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
123 unsigned RegNum; member in struct:__anon2463::LanaiOperand::RegOp
158 return Reg.RegNum;
594 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, argument
597 Op->Reg.RegNum = RegNum;
698 unsigned RegNum; local
705 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier());
706 if (RegNum == 0) {
712 return LanaiOperand::createReg(RegNum, Star
719 ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) argument
730 tryParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp154 unsigned RegNum = MCO.getReg(); local
159 uint32_t Val = RI->getEncodingValue(RegNum);
166 Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp348 unsigned RegNum; member in struct:__anon2167::AArch64Operand::RegOp
374 unsigned RegNum; member in struct:__anon2167::AArch64Operand::VectorListOp
580 return Reg.RegNum;
590 return VectorList.RegNum;
1087 Reg.RegNum) ||
1089 Reg.RegNum));
1164 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
1169 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
1175 Reg.RegNum);
1181 Reg.RegNum);
1881 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg, AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) argument
1900 CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth, SMLoc S, SMLoc E, MCContext &Ctx, AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) argument
1915 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E, MCContext &Ctx) argument
2330 unsigned RegNum = 0; local
2372 tryParseScalarRegister(unsigned &RegNum) argument
3303 unsigned RegNum = matchRegisterNameAlias(Head, MatchKind); local
3328 unsigned RegNum; local
3601 unsigned RegNum; local
3636 unsigned RegNum; local
5688 unsigned RegNum; local
6225 unsigned RegNum; local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp173 unsigned RegNum; member in struct:__anon2638::VEOperand::RegOp
346 return Reg.RegNum;
596 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, argument
599 Op->Reg.RegNum = RegNum;
647 Op.Reg.RegNum = I32Regs[regIdx];
656 Op.Reg.RegNum = F32Regs[regIdx];
665 Op.Reg.RegNum = F128Regs[regIdx / 2];
674 Op.Reg.RegNum = VM512Regs[regIdx / 2];
686 Op.Reg.RegNum
808 int RegNum = matchFn(Name); local
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCRegisterInfo.h513 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
517 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
521 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
525 int getSEHRegNum(MCRegister RegNum) const;
529 int getCodeViewRegNum(MCRegister RegNum) const;
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h903 int64_t RegNum = MatchTable[CurrentIdx++]; local
905 OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
908 << InsnID << "], " << RegNum << ")\n"); local
914 int64_t RegNum = MatchTable[CurrentIdx++]; local
916 OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
919 << InsnID << "], " << RegNum << ")\n"); local
925 int64_t RegNum = MatchTable[CurrentIdx++]; local
928 OutMIs[InsnID].addReg(RegNum, RegFlags);
932 << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp280 auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
282 if (30 == RegNum) {
287 return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp90 unsigned RegNum; member in struct:__anon2357::BPFOperand::RegOp
150 return Reg.RegNum;
209 Op->Reg.RegNum = RegNo;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.h26 const char *getVerboseConditionRegName(unsigned RegNum,
H A DPPCInstPrinter.cpp608 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, argument
613 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp238 unsigned RegNum; member in struct:__anon2602::SparcOperand::RegOp
324 return Reg.RegNum;
438 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, argument
441 Op->Reg.RegNum = RegNum;
471 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
482 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
505 Op.Reg.RegNum = Reg;
518 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DStackMaps.cpp179 int RegNum = TRI->getDwarfRegNum(Reg, false); local
180 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
181 RegNum = TRI->getDwarfRegNum(*SR, false);
183 assert(RegNum >= 0 && "Invalid Dwarf register number.");
184 return (unsigned)RegNum;
633 /// uint16 : Dwarf RegNum
639 /// uint16 : Dwarf RegNum
/netbsd-current/external/apache2/llvm/dist/clang/lib/Basic/
H A DTargetInfo.cpp519 if (AN == Name && ARN.RegNum < Names.size())
560 if (AN == Name && ARN.RegNum < Names.size())
561 return ReturnCanonical ? Names[ARN.RegNum] : Name;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp91 unsigned RegNum; member in struct:__anon2379::CSKYOperand::RegOp
198 return Reg.RegNum;
236 Op->Reg.RegNum = RegNo;

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