/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 109 void PutInWorklist(unsigned RegIdx) { argument 110 if (WorklistMembers.test(RegIdx)) 112 WorklistMembers.set(RegIdx); 113 Worklist.push_back(RegIdx); 360 unsigned RegIdx = Register::virtReg2Index(Reg); local 361 DefinedByCopy.set(RegIdx); 362 PutInWorklist(RegIdx); 493 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { 504 unsigned RegIdx = Worklist.front(); local 539 unsigned RegIdx = Register::virtReg2Index(Reg); local [all...] |
H A D | SplitKit.h | 332 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains: 334 /// 1. No entry - the value is not mapped to Edit.get(RegIdx). 336 /// Edit.get(RegIdx). Each value is represented by a minimal live range at 338 /// of RegIdx in RegAssign. 350 /// getLICalc - Return the LICalc to use for RegIdx. In spill mode, the 353 LiveIntervalCalc &getLICalc(unsigned RegIdx) { argument 354 return LICalc[SpillMode != SM_Partition && RegIdx != 0]; 378 /// defValue - define a value in RegIdx from ParentVNI at Idx. 386 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx, 389 /// forceRecompute - Force the live range of ParentVNI in RegIdx t [all...] |
H A D | SplitKit.cpp | 466 VNInfo *SplitEditor::defValue(unsigned RegIdx, argument 473 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); 482 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); 484 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not 503 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { argument 504 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; 516 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); 550 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { 563 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); 585 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, argument 548 buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRAsmPrinter.cpp | 118 unsigned RegIdx = ByteNumber / BytesPerReg; local 119 assert(RegIdx < NumOpRegs && "Multibyte index out of range."); 121 Reg = MI->getOperand(OpNum + RegIdx).getReg();
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H A D | AVRISelLowering.cpp | 1040 unsigned RegIdx = RegLastIdx + TotalBytes; local 1041 RegLastIdx = RegIdx; 1043 if (RegIdx >= array_lengthof(RegList8)) { 1058 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); 1060 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); 1069 RegIdx -= VT.getStoreSize(); 1106 int RegIdx = TotalBytes - 1; local 1111 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); 1113 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); 1120 RegIdx [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.cpp | 201 unsigned RegIdx = State.getFirstUnallocated(RegList); local 206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) 207 State.AllocateReg(RegList[RegIdx++]); 248 unsigned RegIdx = State.getFirstUnallocated(RegList); local 250 if (RegIdx >= RegList.size()) 253 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
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H A D | ARMISelLowering.cpp | 4300 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); local 4301 if (RegIdx != array_lengthof(GPRArgRegs)) 4302 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 879 struct RegIdxOp RegIdx; member in union:__anon2507::MipsOperand::__anon2508 894 Op->RegIdx.Index = Index; 895 Op->RegIdx.RegInfo = RegInfo; 896 Op->RegIdx.Kind = RegKind; 897 Op->RegIdx.Tok.Data = Str.data(); 898 Op->RegIdx.Tok.Length = Str.size(); 908 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 909 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); 911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64CollectLOH.cpp | 553 int RegIdx = mapRegToGPRIndex(LI.PhysReg); local 554 if (RegIdx >= 0) 555 LOHInfos[RegIdx].OneUser = true;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.h | 35 unsigned getMSACtrlReg(const SDValue RegIdx) const;
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H A D | MipsSEISelDAGToDAG.cpp | 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { 79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); 844 SDValue RegIdx = Node->getOperand(2); local 846 getMSACtrlReg(RegIdx), MVT::i32); 914 SDValue RegIdx = Node->getOperand(2); local 917 getMSACtrlReg(RegIdx), Value);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ExpandPseudo.cpp | 667 for (int64_t OpndIdx = 3, RegIdx = 0; 669 OpndIdx++, RegIdx++) { 671 int64_t Offset = FrameOffset + VarArgsRegsOffset + RegIdx * 16;
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H A D | X86SpeculativeLoadHardening.cpp | 1874 unsigned RegIdx = Log2_32(RegBytes); local 1875 assert(RegIdx < 4 && "Unsupported register size"); 1887 if (RC == NOREXRegClasses[RegIdx]) 1893 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]);
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H A D | X86FastISel.cpp | 2636 unsigned RegIdx = X86::sub_16bit; local 2637 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, RegIdx);
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H A D | X86ISelLowering.cpp | [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/ |
H A D | VarLocBasedImpl.cpp | 1345 LocIndex RegIdx = LocIndex::fromRawInteger(*It); 1346 Collected.push_back(VarLocIDs[RegIdx]);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 2452 unsigned RegIdx = RegNum / AlignSize; local 2461 if (RegIdx >= RC.getNumRegs()) { 2466 return RC.getRegister(RegIdx);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 1880 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); local 1881 if (RegIdx == ArgVGPRs.size()) { 1888 unsigned Reg = ArgVGPRs[RegIdx]; 1902 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); local 1903 if (RegIdx == ArgSGPRs.size()) 1906 unsigned Reg = ArgSGPRs[RegIdx];
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6848 unsigned RegIdx = 3; local 6856 RegIdx = 4; 6858 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 6860 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 6862 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6739 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); local 6741 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
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