/netbsd-current/external/gpl3/gdb.old/dist/sim/testsuite/sim/bfin/ |
H A D | a0.s | 6 R0 = 1; define 7 R0 <<= 1; 8 DBGA ( R0.L , 2 ); 9 R0 <<= 1; 10 DBGA ( R0.L , 4 ); 11 R0 <<= 3; 12 DBGA ( R0.L , 32 ); 13 R0 += 5; 14 DBGA ( R0.L , 37 ); 15 R0 [all...] |
H A D | simple0.s | 7 R0 = 5; define 8 R0 += -1; 9 DBGA ( R0.L , 4 );
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H A D | events.s | 11 R0 = 0; define 15 R0 += 1; # 1 16 R0 += 1; 17 R0 += 1; # 3 18 R0 += 1; 19 R0 += 1; # 5 20 R0 += 1; 21 R0 += 1; # 7 22 R0 += 1; 23 R0 [all...] |
H A D | testset2.s | 15 R0 = 0; define 16 CC = R0; 17 R0 = B [ P0 ] (Z); define 18 DBGA ( R0.L , 0 ); 20 R0 = CC; define 21 DBGA ( R0.L , 1 ); 22 R0 = B [ P0 ] (Z); define 23 DBGA ( R0.L , 0x80 ); 25 R0 = 0; define 26 CC = R0; 28 R0 = CC; define 30 R0 = B [ P0 ] (Z); define [all...] |
H A D | b0.S | 7 R0 = 0; define 8 ASTAT = R0; 10 CC = R0 == R0; 14 R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); define 15 R0 = R0 + R0; define 16 R0 define 19 R0 = ASTAT; CHECKREG R0, (_CC|_AN); define 20 R0 = - R0; define 21 R0 = ASTAT; CHECKREG R0, (_CC|_AN); define 25 R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); define 29 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); define 33 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); define 37 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN); define 45 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ); define 49 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ); define [all...] |
H A D | a2.s | 8 R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); define 9 R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); define 10 R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); define 11 R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); define 12 R0 = [ P0 + 16 ]; DBGA ( R0 define 13 R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); define 14 R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); define 15 R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); define 17 R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); define 18 R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); define 19 R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); define 20 R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); define 21 R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); define 22 R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); define 23 R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); define 24 R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); define 28 R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); define 29 R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); define 30 R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); define 31 R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); define 32 R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); define 33 R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); define 34 R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); define 35 R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); define 36 R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); define 37 R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); define 38 R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); define 39 R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); define 40 R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); define 41 R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); define 42 R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); define 43 R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); define 45 R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); define 46 R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); define 47 R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); define 48 R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); define 49 R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); define 50 R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); define 51 R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); define 52 R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); define 53 R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); define 54 R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); define 55 R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); define 56 R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); define 57 R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); define 58 R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); define 59 R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); define 60 R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); define 61 R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); define 62 R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); define 63 R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); define 64 R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); define 65 R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); define 66 R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); define 67 R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); define 68 R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); define 69 R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); define 70 R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); define 71 R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); define 72 R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); define 73 R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); define [all...] |
H A D | issue113.s | 7 R0.L = 0x10; 8 A0.x = R0; 10 R0.L = 0x0038; 11 R0.H = 0x0006; 13 R0.L = SIGNBITS A0; 15 DBGA ( R0.L , 0xfffa ); 16 DBGA ( R0.H , 0x0006 );
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H A D | issue175.s | 6 R0 = 0; define 7 ASTAT = R0; 9 imm32 R0, 0x00010001; 10 R0 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); define 11 _DBG R0; 13 CHECKREG R0, 0x80007fff; 16 R0 = ASTAT; define 18 DBGA ( R0 21 R0 = 0; define [all...] |
H A D | a1.s | 7 R0 = 63; define 8 DBGA ( R0.L , 63 ); 9 R0 = -64; define 10 DBGA ( R0.L , 0xffc0 ); 12 R0 = P0; DBGA ( R0.L , 63 ); define 14 R0 = P0; DBGA ( R0.L , 0xffc0 ); define 17 R0.L = 0x1111; 18 DBGA ( R0 24 R0 = P0; DBGA ( R0.L , 0x2222 ); define 27 R0 = P0; DBGA ( R0.H , 0x2222 ); define [all...] |
H A D | issue127.s | 7 R0.L = 0x5d8c; 8 R0.H = 0x90c4; 9 A0.w = R0; 10 R0.L = 0x8308; 11 A0.x = R0; 12 R0.L = 0x32da; 13 R0.H = 0xa6ec; 14 A1.w = R0; 15 R0.L = 0x1772; 16 A1.x = R0; 32 R0 = A0.x; DBGA ( R0.L , 0 ); define 33 R0 = A1.x; DBGA ( R0.L , 0 ); define [all...] |
H A D | s0.s | 6 R0 = 10; define 7 P0 = R0; 10 R0 += -1; 11 DBGA ( R0.L , 0 );
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/netbsd-current/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
H A D | a0.s | 6 R0 = 1; define 7 R0 <<= 1; 8 DBGA ( R0.L , 2 ); 9 R0 <<= 1; 10 DBGA ( R0.L , 4 ); 11 R0 <<= 3; 12 DBGA ( R0.L , 32 ); 13 R0 += 5; 14 DBGA ( R0.L , 37 ); 15 R0 [all...] |
H A D | simple0.s | 7 R0 = 5; define 8 R0 += -1; 9 DBGA ( R0.L , 4 );
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H A D | events.s | 11 R0 = 0; define 15 R0 += 1; # 1 16 R0 += 1; 17 R0 += 1; # 3 18 R0 += 1; 19 R0 += 1; # 5 20 R0 += 1; 21 R0 += 1; # 7 22 R0 += 1; 23 R0 [all...] |
H A D | testset2.s | 15 R0 = 0; define 16 CC = R0; 17 R0 = B [ P0 ] (Z); define 18 DBGA ( R0.L , 0 ); 20 R0 = CC; define 21 DBGA ( R0.L , 1 ); 22 R0 = B [ P0 ] (Z); define 23 DBGA ( R0.L , 0x80 ); 25 R0 = 0; define 26 CC = R0; 28 R0 = CC; define 30 R0 = B [ P0 ] (Z); define [all...] |
H A D | b0.S | 7 R0 = 0; define 8 ASTAT = R0; 10 CC = R0 == R0; 14 R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); define 15 R0 = R0 + R0; define 16 R0 define 19 R0 = ASTAT; CHECKREG R0, (_CC|_AN); define 20 R0 = - R0; define 21 R0 = ASTAT; CHECKREG R0, (_CC|_AN); define 25 R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); define 29 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); define 33 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); define 37 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN); define 45 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ); define 49 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ); define [all...] |
H A D | a2.s | 8 R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); define 9 R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); define 10 R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); define 11 R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); define 12 R0 = [ P0 + 16 ]; DBGA ( R0 define 13 R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); define 14 R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); define 15 R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); define 17 R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); define 18 R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); define 19 R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); define 20 R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); define 21 R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); define 22 R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); define 23 R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); define 24 R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); define 28 R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); define 29 R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); define 30 R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); define 31 R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); define 32 R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); define 33 R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); define 34 R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); define 35 R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); define 36 R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); define 37 R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); define 38 R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); define 39 R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); define 40 R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); define 41 R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); define 42 R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); define 43 R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); define 45 R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); define 46 R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); define 47 R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); define 48 R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); define 49 R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); define 50 R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); define 51 R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); define 52 R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); define 53 R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); define 54 R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); define 55 R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); define 56 R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); define 57 R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); define 58 R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); define 59 R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); define 60 R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); define 61 R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); define 62 R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); define 63 R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); define 64 R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); define 65 R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); define 66 R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); define 67 R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); define 68 R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); define 69 R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); define 70 R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); define 71 R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); define 72 R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); define 73 R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); define [all...] |
H A D | issue113.s | 7 R0.L = 0x10; 8 A0.x = R0; 10 R0.L = 0x0038; 11 R0.H = 0x0006; 13 R0.L = SIGNBITS A0; 15 DBGA ( R0.L , 0xfffa ); 16 DBGA ( R0.H , 0x0006 );
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H A D | issue175.s | 6 R0 = 0; define 7 ASTAT = R0; 9 imm32 R0, 0x00010001; 10 R0 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); define 11 _DBG R0; 13 CHECKREG R0, 0x80007fff; 16 R0 = ASTAT; define 18 DBGA ( R0 21 R0 = 0; define [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/mt/ |
H A D | allinsn.d | 10 0: 00 00 00 00 add R0,R0,R0 13 4: 02 00 00 00 addu R0,R0,R0 16 8: 01 00 00 00 addi R0,R0,#\$0 19 c: 03 00 00 00 addui R0,R0,#\ [all...] |
H A D | msys.d | 10 0: 80 00 00 00 ldctxt R0,R0,#\$0,#\$0,#\$0 11 4: 84 00 00 00 ldfb R0,R0,#\$0 12 8: 88 00 00 00 stfb R0,R0,#\$0 13 c: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 14 10: 90 00 00 00 mfbcb R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0 15 14: 94 00 00 00 fbcci R0,#\ [all...] |
H A D | allinsn.s | 8 add R0,R0,R0 12 addu R0,R0,R0 16 addi R0,R0,#0 20 addui R0,R0,# [all...] |
H A D | msys.s | 3 ; Make sure that each mnemonic gives the proper opcode. Use R0 and #0 7 ldctxt R0,R0,#0,#0,#0 8 ldfb R0,R0,#0 9 stfb R0, R0, #0 10 fbcb R0,#0,#0,#0,#0,#0,#0,#0,#0 11 mfbcb R0,#0,R0,# [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/bfin/ |
H A D | expected_move_errors.s | 3 R0.L = A1; 4 R0.H = A0; 5 R0 = A1; define
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/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/tic4x/ |
H A D | addressing.s | 43 Type_CI:ldiu R0,R0 ; Unconditional load (00000) 44 ldic R0,R0 ; Carry load (00001) 45 ldilo R0,R0 ; Lower than load (00001) 46 ldils R0,R0 ; Lower than or same load (00010) 47 ldihi R0,R0 ; Highe [all...] |