Searched refs:PhysReg (Results 1 - 25 of 85) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp17 for (const size_t PhysReg : SourceBits.set_bits()) {
19 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid();
35 for (MCPhysReg PhysReg : RegClass)
36 if (!ReservedReg[PhysReg]) // Removing reserved registers.
37 SourceBits.set(PhysReg);
42 const MCPhysReg PhysReg)
44 SourceBits.set(PhysReg);
51 for (const size_t PhysReg : SourceBits.set_bits()) {
52 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid();
55 Origins[*Itr] = PhysReg;
41 RegisterAliasingTracker(const MCRegisterInfo &RegInfo, const MCPhysReg PhysReg) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h88 /// assigned to PhysReg or its aliases. This interference could be resolved
98 /// regmask operand that doesn't preserve PhysReg. This typically means
99 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
103 /// Check for interference before assigning VirtReg to PhysReg.
104 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
107 InterferenceKind checkInterference(LiveInterval &VirtReg, MCRegister PhysReg);
110 /// assignment to PhysReg. If this function returns true, there is
112 /// assigned to PhysReg. If this function returns false, PhysReg is free at
114 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
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H A DLiveIntervalCalc.h54 void extendToUses(LiveRange &LR, MCRegister PhysReg) { argument
55 extendToUses(LR, PhysReg, LaneBitmask::getAll());
H A DReachingDefAnalysis.h141 /// PhysReg that reaches MI, relative to the begining of MI's basic block.
142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
144 /// Return whether A and B use the same def of PhysReg.
146 MCRegister PhysReg) const;
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
152 /// Return the local MI that produces the live out value for PhysReg, or
155 MCRegister PhysReg) const;
160 MCRegister PhysReg) const;
172 bool hasLocalDefBefore(MachineInstr *MI, MCRegister PhysReg) const;
176 bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) cons
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H A DRegisterClassInfo.h114 /// overlaps PhysReg, or NoRegister if Reg doesn't overlap a
116 MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
117 if (PhysReg.id() < CalleeSavedAliases.size())
118 return CalleeSavedAliases[PhysReg];
H A DLiveRangeCalc.h149 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
151 unsigned PhysReg, ArrayRef<SlotIndex> Undefs);
207 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
208 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DReachingDefAnalysis.cpp33 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg) { argument
34 return isValidRegUse(MO) && MO.getReg() == PhysReg;
41 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg) { argument
42 return isValidRegDef(MO) && MO.getReg() == PhysReg;
62 for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) {
258 MCRegister PhysReg) const {
266 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
279 MCRegister PhysReg) const {
280 return hasLocalDefBefore(MI, PhysReg)
281 ? getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg))
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H A DLiveRegMatrix.cpp81 LiveInterval &VRegInterval, MCRegister PhysReg,
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { argument
106 << printReg(PhysReg, TRI) << ':');
108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg);
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); local
124 << " from " << printReg(PhysReg, TRI) << ':');
127 foreachUnit(TRI, VirtReg, PhysReg,
80 foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, MCRegister PhysReg, Callable Func) argument
146 checkRegMaskInterference(LiveInterval &VirtReg, MCRegister PhysReg) argument
164 checkRegUnitInterference(LiveInterval &VirtReg, MCRegister PhysReg) argument
186 checkInterference(LiveInterval &VirtReg, MCRegister PhysReg) argument
209 checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg) argument
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H A DRegAllocFast.cpp91 MCPhysReg PhysReg = 0; ///< Currently held here. member in struct:__anon1856::RegAllocFast::LiveReg
153 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
154 bool isPhysRegFree(MCPhysReg PhysReg) const;
157 void markRegUsedInInstr(MCPhysReg PhysReg) { argument
158 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
163 bool isClobberedByRegMasks(MCPhysReg PhysReg) const {
164 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) {
165 return MachineOperand::clobbersPhysReg(Mask, PhysReg);
170 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { argument
171 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
184 markPhysRegUsedInInstr(MCPhysReg PhysReg) argument
190 unmarkRegUsedInInstr(MCPhysReg PhysReg) argument
293 setPhysRegState(MCPhysReg PhysReg, unsigned NewState) argument
460 reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg) argument
521 MCPhysReg PhysReg = LR.PhysReg; local
563 displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) argument
593 freePhysReg(MCPhysReg PhysReg) argument
675 assignVirtToPhysReg(MachineInstr &AtMI, LiveReg &LR, MCPhysReg PhysReg) argument
825 MCPhysReg PhysReg; local
905 MCPhysReg PhysReg = LRI->PhysReg; local
979 setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg) argument
1046 MCPhysReg PhysReg = LR.PhysReg; local
1284 MCPhysReg PhysReg = LR.PhysReg; local
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H A DRegisterClassInfo.cpp113 unsigned PhysReg = RawOrder[i]; local
115 if (Reserved.test(PhysReg))
117 uint8_t Cost = RegCosts[PhysReg];
120 if (CalleeSavedAliases[PhysReg] &&
121 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
122 // PhysReg aliases a CSR, save it for later.
123 CSRAlias.push_back(PhysReg);
127 RCI.Order[N++] = PhysReg;
136 unsigned PhysReg = CSRAlias[i]; local
137 uint8_t Cost = RegCosts[PhysReg];
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H A DRegAllocBasic.cpp122 bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
206 // Spill or split all live virtual registers currently unified under PhysReg
209 bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg, argument
216 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
226 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
230 // Spill each interfering vreg allocated to PhysReg or an alias.
269 for (MCRegister PhysReg : Order) {
270 assert(PhysReg.isValid());
271 // Check for interference in PhysReg
272 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
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H A DRegisterCoalescer.h64 CoalescerPair(Register VirtReg, MCRegister PhysReg, argument
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
H A DRegAllocGreedy.cpp300 /// be mapped to the evictor Vreg and the PhysReg it was evicted from.
316 /// \param PhysReg The physical register Evictee was evicted from.
319 void addEviction(MCRegister PhysReg, Register Evictor, Register Evictee) { argument
321 Evictees[Evictee].second = PhysReg;
324 /// Return the Evictor Vreg which evicted Evictee Vreg from PhysReg.
326 /// \return The Evictor vreg which evicted Evictee vreg from PhysReg. 0 if
327 /// nobody has evicted Evictee from PhysReg.
353 MCRegister PhysReg; member in struct:__anon1858::RAGreedy::GlobalSplitCandidate
358 // Interference for PhysReg.
366 PhysReg
538 MCRegister PhysReg; member in struct:__anon1858::RAGreedy::HintInfo
540 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg) argument
803 MCRegister PhysReg; local
856 MCRegister PhysReg; local
917 canEvictInterference( LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) const argument
1015 canEvictInterferenceInRange(const LiveInterval &VirtReg, MCRegister PhysReg, SlotIndex Start, SlotIndex End, EvictionCost &MaxCost) const argument
1093 evictInterference(LiveInterval &VirtReg, MCRegister PhysReg, SmallVectorImpl<Register> &NewVRegs) argument
1189 MCRegister PhysReg = *I; local
1528 MCRegister PhysReg = VregEvictorInfo.second; local
2158 calcGapWeights(MCRegister PhysReg, SmallVectorImpl<float> &GapWeight) argument
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H A DInterferenceCache.h44 /// of PhysReg in all basic blocks.
46 /// PhysReg - The register currently represented.
47 MCRegister PhysReg = 0; member in class:llvm::InterferenceCache::Entry
68 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
90 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
105 PhysReg = MCRegister::NoRegister;
111 MCRegister getPhysReg() const { return PhysReg; }
154 // get - Get a valid entry for PhysReg.
155 Entry *get(MCRegister PhysReg);
207 /// setPhysReg - Point this cursor to PhysReg'
208 setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) argument
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H A DVirtRegMap.cpp190 void addLiveInsForSubRanges(const LiveInterval &LI, MCRegister PhysReg) const;
279 MCRegister PhysReg) const {
318 MBB->addLiveIn(PhysReg, LaneMask);
333 // assigned PhysReg must be marked as live-in to those blocks.
334 Register PhysReg = VRM->getPhys(VirtReg); local
335 if (PhysReg == VirtRegMap::NO_PHYS_REG) {
343 addLiveInsForSubRanges(LI, PhysReg);
353 MBB->addLiveIn(PhysReg);
359 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
544 MCRegister PhysReg local
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H A DInterferenceCache.cpp63 InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) { argument
64 unsigned char E = PhysRegEntries[PhysReg.id()];
65 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
81 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
82 PhysRegEntries[PhysReg] = E;
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
107 PhysReg = physReg;
113 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
122 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
194 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
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H A DLiveRangeCalc.cpp89 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, argument
107 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs))
194 SlotIndex Use, unsigned PhysReg,
214 errs() << "Use of " << printReg(PhysReg, MRI->getTargetRegisterInfo())
222 if (Register::isPhysicalRegister(PhysReg) && !MBB->isLiveIn(PhysReg)) {
225 errs() << "The register " << printReg(PhysReg, TRI)
193 findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use, unsigned PhysReg, ArrayRef<SlotIndex> Undefs) argument
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
104 if (!MRI->isPhysRegUsed(PhysReg) &&
105 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) {
106 Matrix->assign(LI, PhysReg);
107 assert(PhysReg != 0);
131 Register PhysReg = VRM->getPhys(VirtReg); local
134 PhysReg = TRI->getSubReg(PhysReg, SubReg);
138 MO.setReg(PhysReg);
150 const Register PhysReg local
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H A DGCNNSAReassign.cpp176 Register PhysReg = VRM->getPhys(Reg);
179 if (!PhysReg)
203 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
210 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
219 VgprBase = PhysReg;
220 else if (VgprBase + I != PhysReg)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVERegisterInfo.h33 bool isConstantPhysReg(MCRegister PhysReg) const override;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h34 MCRegister PhysReg) const override;
36 bool isConstantPhysReg(MCRegister PhysReg) const override;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp109 virtual void markPhysRegUsed(unsigned PhysReg) { argument
110 MIRBuilder.getMRI()->addLiveIn(PhysReg);
111 MIRBuilder.getMBB().addLiveIn(PhysReg);
128 void markPhysRegUsed(unsigned PhysReg) override {
129 MIB.addDef(PhysReg, RegState::Implicit);
140 Register PhysReg = VA.getLocReg(); local
141 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
146 auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1)));
147 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg
242 Register PhysReg = VA.getLocReg(); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallLowering.cpp107 void assignValueToReg(Register ValVReg, Register PhysReg,
109 MIB.addUse(PhysReg, RegState::Implicit);
111 MIRBuilder.buildCopy(PhysReg, ExtReg);
198 void assignValueToReg(Register ValVReg, Register PhysReg,
200 markPhysRegUsed(PhysReg); variable
201 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
207 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
217 void markPhysRegUsed(unsigned PhysReg) override {
218 MIRBuilder.getMRI()->addLiveIn(PhysReg); variable
219 MIRBuilder.getMBB().addLiveIn(PhysReg); variable
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp111 void assignValueToReg(Register ValVReg, Register PhysReg,
114 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
120 MIRBuilder.buildCopy(PhysReg, ExtReg);
121 MIB.addUse(PhysReg, RegState::Implicit);
282 void assignValueToReg(Register ValVReg, Register PhysReg,
285 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
293 markPhysRegUsed(PhysReg); variable
295 MIRBuilder.buildCopy(ValVReg, PhysReg);
302 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
346 virtual void markPhysRegUsed(unsigned PhysReg)
355 MIRBuilder.getMBB().addLiveIn(PhysReg); variable
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp42 Register PhysReg = VRM->getPhys(MO.getReg()); local
43 if (SystemZ::GR32BitRegClass.contains(PhysReg))
45 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
110 Register PhysReg = Register::isPhysicalRegister(Reg)
113 if (PhysReg) {
115 PhysReg = getSubReg(PhysReg, MO->getSubReg());
117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
119 if (!MRI->isReserved(PhysReg)
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