Searched refs:PSC_LEV5_IER (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/arch/mac68k/include/
H A Dpsc.h95 #define PSC_LEV5_IER 0x154 /* level 5 interrupt enable register */ macro
/netbsd-current/sys/arch/mac68k/mac68k/
H A Dpsc.c237 intbits &= 0x3 & psc_reg1(PSC_LEV5_IER);

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