Searched refs:PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT (Results 1 - 1 of 1) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ | ||
| H A D | bif_5_0_sh_mask.h | 10236 #define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb macro |
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