/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===// 32 ArrayRef<MCPhysReg> Order; member in class:llvm::AllocationOrder 33 // How far into the Order we can iterate. This is 0 if the AllocationOrder is 34 // constructed with HardHints = true, Order.size() otherwise. While 37 // avoid warnings and under the assumption that the size of Order is 59 return AO.Order[Pos]; 67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos])) 88 /// Create an AllocationOrder given the Hits, Order, and HardHits values. 90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, 92 : Hints(std::move(Hints)), Order(Orde [all...] |
H A D | AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); local 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); 49 assert(is_contained(Order, Hints[I]) && 52 return AllocationOrder(std::move(Hints), Order, HardHints);
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H A D | RegisterClassInfo.cpp | 100 if (!RCI.Order) 101 RCI.Order.reset(new MCPhysReg[NumRegs]); 127 RCI.Order[N++] = PhysReg; 140 RCI.Order[N++] = PhysReg; 160 dbgs() << ' ' << printReg(RCI.Order[I], TRI);
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H A D | RegAllocGreedy.cpp | 461 const AllocationOrder &Order); 464 const AllocationOrder &Order); 466 const AllocationOrder &Order, 478 MCRegister getCheapestEvicteeWeight(const AllocationOrder &Order, 498 AllocationOrder &Order, 509 AllocationOrder &Order, MCRegister PhysReg, 800 AllocationOrder &Order, 804 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { 821 if (Order 799 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs, const SmallVirtRegSet &FixedRegisters) argument 854 auto Order = local 1067 getCheapestEvicteeWeight(const AllocationOrder &Order, const LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) const argument 1150 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs, uint8_t CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) argument 1522 splitCanCauseEvictionChain(Register Evictee, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) argument 1581 splitCanCauseLocalSpill(unsigned VirtRegToSplit, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) argument 1604 calcGlobalSplitCost(GlobalSplitCandidate &Cand, const AllocationOrder &Order, bool *CanCauseEvictionChain) argument 1836 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument 1880 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) argument 2027 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument 2093 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument 2236 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument [all...] |
H A D | LocalStackSlotAllocation.cpp | 56 // Order reference instruction appears in program. Used to ensure 59 unsigned Order; member in class:__anon1794::FrameRef 63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} 66 return std::tie(LocalOffset, FrameIdx, Order) < 67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); 302 unsigned Order = 0; local 330 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++));
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/netbsd-current/external/apache2/llvm/dist/libcxx/benchmarks/ |
H A D | algorithms.bench.cpp | 35 enum class Order { class in namespace:__anon1225 43 struct AllOrders : EnumValuesAsTuple<AllOrders, Order, 6> { 50 void fillValues(std::vector<T>& V, size_t N, Order O) { 51 if (O == Order::SingleElement) { 60 void fillValues(std::vector<std::pair<T, T> >& V, size_t N, Order O) { 61 if (O == Order::SingleElement) { 75 void fillValues(std::vector<std::tuple<T1, T2, T3> >& V, size_t N, Order O) { 76 if (O == Order::SingleElement) { 96 void fillValues(std::vector<std::string>& V, size_t N, Order O) { 97 if (O == Order [all...] |
H A D | map.bench.cpp | 45 enum class Order { Sorted, Random }; class in namespace:__anon1229 46 struct AllOrders : EnumValuesAsTuple<AllOrders, Order, 2> { 236 template <class Mode, class Order> 243 Order::value == ::Order::Random ? Shuffle::Keys : Shuffle::None, 1000); 264 Order::value == ::Order::Random ? Shuffle::Keys 272 return "BM_Insert" + baseName() + Mode::name() + Order::name(); 355 template <class Mode, class Order> 362 Order [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Support/ |
H A D | DynamicLibrary.cpp | 74 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { argument 75 if (Order & SO_LoadOrder) { 89 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { argument 90 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && 93 if (!Process || (Order & SO_LoadedFirst)) { 94 if (void *Ptr = LibLookup(Symbol, Order)) 103 if (Order & SO_LoadedLast) { 104 if (void *Ptr = LibLookup(Symbol, Order))
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/netbsd-current/external/gpl3/gcc.old/dist/libphobos/src/std/digest/ |
H A D | digest.d | 15 alias Order = _newDigest.Order;
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H A D | package.d | 495 char[digestLength!(Hash)*2] hexDigest(Hash, Order order = Order.increasing, Range)(ref Range range) 517 char[digestLength!(Hash)*2] hexDigest(Hash, Order order = Order.increasing, T...)(scope const T data) 527 assert(hexDigest!(CRC32, Order.decreasing)("The quick brown fox jumps over the lazy dog") == "414FA339"); 533 assert(hexDigest!(CRC32, Order.decreasing)("The quick ", "brown ", "fox jumps over the lazy dog") == "414FA339"); 683 enum Order : bool 696 * opposite order, pass Order.decreasing as a parameter. 707 char[num*2] toHexString(Order order = Order [all...] |
/netbsd-current/games/mille/ |
H A D | varpush.c | 59 { (void *) &Order, sizeof Order },
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/netbsd-current/external/gpl3/gcc/dist/libphobos/src/std/digest/ |
H A D | package.d | 546 char[digestLength!(Hash)*2] hexDigest(Hash, Order order = Order.increasing, Range)(ref Range range) 568 char[digestLength!(Hash)*2] hexDigest(Hash, Order order = Order.increasing, T...)(scope const T data) 578 assert(hexDigest!(CRC32, Order.decreasing)("The quick brown fox jumps over the lazy dog") == "414FA339"); 584 assert(hexDigest!(CRC32, Order.decreasing)("The quick ", "brown ", "fox jumps over the lazy dog") == "414FA339"); 734 enum Order : bool 746 assert(crc32.toHexString!(Order.decreasing) == "414FA339"); 747 assert(crc32.toHexString!(LetterCase.lower, Order.decreasing) == "414fa339"); 757 * opposite order, pass Order [all...] |
/netbsd-current/usr.sbin/ypserv/yptest/ |
H A D | yptest.c | 54 int KeyLen, ValLen, Status, Order; local 104 Status = yp_order(Domain, Map, &Order); 106 printf("%d\n", Order);
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | RuntimeLibcalls.h | 66 Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT);
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H A D | RegisterClassInfo.h | 37 std::unique_ptr<MCPhysReg[]> Order; member in struct:llvm::RegisterClassInfo::RCInfo 42 return makeArrayRef(Order.get(), NumRegs);
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H A D | SelectionDAGNodes.h | 708 void setIROrder(unsigned Order) { IROrder = Order; } argument 1056 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs) 1058 IROrder(Order), debugLoc(std::move(dl)) { 1087 SDLoc(const Instruction *I, int Order) : IROrder(Order) { argument 1088 assert(Order >= 0 && "bad IROrder"); 1234 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT, 1256 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, 1396 AtomicSDNode(unsigned Opc, unsigned Order, cons argument 1450 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) argument 1482 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M) argument 1740 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, int64_t Size, int64_t Offset) argument 1775 PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl, SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr) argument 2130 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L) argument 2220 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument 2254 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument 2282 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument 2314 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument 2356 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool IsExpanding, EVT MemVT, MachineMemOperand *MMO) argument 2385 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, EVT MemVT, MachineMemOperand *MMO) argument 2421 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument 2466 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ETy) argument 2491 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTrunc) argument 2522 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs) argument 2581 AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A) argument [all...] |
H A D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind 89 /// Additional information about Order dependencies. 124 : Dep(S, Order), Contents(), Latency(0) { 165 /// Tests if this is an Order dependence between two memory accesses 169 return getKind() == Order && (Contents.OrdKind == MayAliasMem 173 /// Tests if this is an Order dependence that is marked as a barrier. 175 return getKind() == Order && Contents.OrdKind == Barrier; 183 /// Tests if this is an Order dependence that is marked as 187 return getKind() == Order && Contents.OrdKind == MustAliasMem; 195 return getKind() == Order [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SDNodeDbgValue.h | 148 unsigned Order; member in class:llvm::SDDbgValue 162 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect), 218 unsigned getOrder() const { return Order; } 244 unsigned Order; member in class:llvm::SDDbgLabel 248 : Label(Label), DL(std::move(dl)), Order(O) {} 258 unsigned getOrder() const { return Order; }
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H A D | ScheduleDAGSDNodes.cpp | 738 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { 761 if (Order != 0 && DVOrder != Order) 786 unsigned Order = N->getIROrder(); 787 if (!Order || Seen.count(Order)) { 794 // If a new instruction was generated for this Order number, record it. 799 Seen.insert(Order); 800 Orders.push_back({Order, NewInsn}); 805 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/tools/llvm-profgen/ |
H A D | CSPreInliner.cpp | 44 std::vector<StringRef> Order; local 53 Order.push_back(Node->Name); 57 std::reverse(Order.begin(), Order.end()); 59 return Order;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
H A D | StructurizeCFG.cpp | 251 SmallVector<RegionNode *, 8> Order; member in class:__anon3027::StructurizeCFG 373 Order.resize(std::distance(GraphTraits<Region *>::nodes_begin(ParentRegion), 375 if (Order.empty()) 381 // A list of range indices of SCCs in Order, to be processed. 383 unsigned I = 0, E = Order.size(); 399 // Add the SCC nodes to the Order array. 402 Order[I++] = N.first; 417 Nodes.insert(Order.begin() + I, Order.begin() + E - 1); 420 EntryNode.first = Order[ [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, argument 64 for (MCPhysReg Reg : Order) 68 for (MCPhysReg Reg : Order) 75 Register VirtReg, ArrayRef<MCPhysReg> Order, 83 VirtReg, Order, Hints, MF, VRM, Matrix); 127 for (MCPhysReg OrderReg : Order) 157 addHints(Order, Hints, RC, MRI); 178 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); 74 getRegAllocationHints( Register VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64RegisterBankInfo.h | 70 ArrayRef<PartialMappingIdx> Order);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.h | 148 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
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/netbsd-current/external/apache2/llvm/dist/clang/lib/CodeGen/ |
H A D | CGAtomic.cpp | 515 uint64_t Size, llvm::AtomicOrdering Order, 529 FailureOrder, Size, Order, Scope); 534 FailureOrder, Size, Order, Scope); 540 Val1, Val2, FailureOrder, Size, Order, Scope); 554 FailureOrder, Size, Order, Scope); 559 FailureOrder, Size, Order, Scope); 571 Load->setAtomic(Order, Scope); 583 Store->setAtomic(Order, Scope); 674 CGF.Builder.CreateAtomicRMW(Op, Ptr.getPointer(), LoadVal1, Order, Scope); 705 uint64_t Size, llvm::AtomicOrdering Order, 512 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, Address Ptr, Address Val1, Address Val2, llvm::Value *IsWeak, llvm::Value *FailureOrder, uint64_t Size, llvm::AtomicOrdering Order, llvm::SyncScope::ID Scope) argument 702 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *Expr, Address Dest, Address Ptr, Address Val1, Address Val2, llvm::Value *IsWeak, llvm::Value *FailureOrder, uint64_t Size, llvm::AtomicOrdering Order, llvm::Value *Scope) argument 829 llvm::Value *Order = EmitScalarExpr(E->getOrder()); local [all...] |