| /netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/arm/ |
| H A D | armv8_2-a.s | 11 .macro test_sysreg Opc1 CRn CRm Opc2 rw
12 mrc p15, \Opc1,\() r0, \CRn\(), \CRm\(), \Opc2\()
14 mcr p15, \Opc1\(), r1, \CRn\(), \CRm\(), \Opc2\()
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 93 unsigned Opc1, Opc2; local
98 Opc1 = PPC::ADDItlsgdL;
102 Opc1 = PPC::ADDItlsldL;
106 Opc1 = PPC::ADDItlsgdL32;
110 Opc1 = PPC::ADDItlsldL32;
125 Opc1 = PPC::PADDI8pc;
158 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
162 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
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| H A D | PPCISelDAGToDAG.cpp | 5742 unsigned Opc1, Opc2, Opc3;
5746 Opc1 = PPC::VSPLTISB;
5751 Opc1 = PPC::VSPLTISH;
5757 Opc1 = PPC::VSPLTISW;
5771 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5783 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5785 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5797 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5799 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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| H A D | Mips16ISelLowering.cpp | 571 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, argument
609 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
636 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, argument
675 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.cpp | 1444 unsigned Opc1 = MI1->getOpcode(); local
1447 if (!isDGEMM(Opc) && isDGEMM(Opc1)) {
1452 (Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_e64 ||
1453 Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64))
1456 switch (Opc1) {
1488 switch (Opc1) {
|
| H A D | SIInstrInfo.cpp | 85 unsigned Opc1 = N1->getMachineOpcode(); local
88 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
136 unsigned Opc1 = Load1->getMachineOpcode(); local
139 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
142 if (isDS(Opc0) && isDS(Opc1)) {
156 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
165 Offset1Idx -= get(Opc1).NumDefs;
171 if (isSMRD(Opc0) && isSMRD(Opc1)) {
174 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
197 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBU
[all...] |
| /netbsd-current/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ContainerModeling.cpp | 140 BinaryOperator::Opcode Opc1,
974 BinaryOperator::Opcode Opc1,
978 return compare(State, Pos.getOffset(), Offset1, Opc1) &&
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 1919 BinaryOperator::BinaryOps Opc1 = B1->getOpcode(); local
1921 if (ConstantsAreOp1 && Opc0 != Opc1) {
1925 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl)
1933 Opc1 = AltB1.Opcode;
1938 if (Opc0 != Opc1)
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6552 unsigned Opc1 = Load1->getMachineOpcode(); local
6554 switch (Opc1) {
6753 unsigned Opc1 = Load1->getMachineOpcode(); local
6755 if (Opc1 != Opc2)
6758 switch (Opc1) {
|
| H A D | X86ISelLowering.cpp | 25079 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
25080 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
25101 Opc = IntrData->Opc1;
25112 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
25113 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
25135 Opc = IntrData->Opc1;
25156 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
25157 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
25191 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
25217 Opc = IntrData->Opc1;
[all...] |
| H A D | X86IntrinsicsInfo.h | 47 uint16_t Opc1; member in struct:llvm::IntrinsicData
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 409 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; local
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
|
| /netbsd-current/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 7358 Value *Opc1 = EmitScalarExpr(E->getArg(1));
7367 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm});
7385 Value *Opc1 = EmitScalarExpr(E->getArg(1));
7387 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm});
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