Searched refs:Op2 (Results 1 - 25 of 114) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.h25 uint64_t Op2; member in struct:llvm::AArch64_IMM::ImmInsnModel
H A DAArch64SelectionDAGInfo.h28 SDValue Chain, SDValue Op1, SDValue Op2,
H A DSVEIntrinsicOpts.cpp290 IntrinsicInst *Op2 = dyn_cast<IntrinsicInst>(I->getArgOperand(1)); local
292 if (Op1 && Op2 &&
294 Op2->getIntrinsicID() == Intrinsic::aarch64_sve_convert_to_svbool &&
295 Op1->getArgOperand(0)->getType() == Op2->getArgOperand(0)->getType()) {
297 Value *Ops[] = {Op1->getArgOperand(0), Op2->getArgOperand(0)};
308 if (Op1 != Op2 && Op2->use_empty())
309 Op2->eraseFromParent();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp142 const MCOperand Op2 = Inst.getOperand(2); local
145 ((Op2.isImm() && Op2.getImm() != 0) ||
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
154 (Op2.isReg() && Op2
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
H A DWebAssemblySelectionDAGInfo.cpp37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2,
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3,
36 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool IsVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
H A DWebAssemblyPeephole.cpp164 const auto &Op2 = MI.getOperand(2); local
165 if (!Op2.isReg())
170 Register NewReg = Op2.getReg();
/netbsd-current/sys/arch/arm/samsung/
H A Dsmc.h63 #define SMC_REG_ID_CP15(CRn, Op1, CRm, Op2) \
65 ((CRn) << 10) | ((Op1) << 7) | ((CRm) << 3) | (Op2))
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument
253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument
268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
346 unsigned Op1, Op2; local
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
359 unsigned Op1, Op2; local
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
365 DecodeGRRegsRegisterClass(Inst, Op2, Addres
372 unsigned Op1, Op2; local
385 unsigned Op1, Op2; local
399 unsigned Op1, Op2; local
412 unsigned Op1, Op2; local
425 unsigned Op1, Op2; local
510 unsigned Op1, Op2; local
524 unsigned Op1, Op2; local
538 unsigned Op1, Op2, Op3; local
551 unsigned Op1, Op2, Op3; local
564 unsigned Op1, Op2, Op3; local
577 unsigned Op1, Op2, Op3; local
590 unsigned Op1, Op2, Op3; local
604 unsigned Op1, Op2, Op3; local
619 unsigned Op1, Op2, Op3; local
633 unsigned Op1, Op2, Op3; local
647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
681 unsigned Op1, Op2, Op3, Op4, Op5; local
701 unsigned Op1, Op2, Op3; local
720 unsigned Op1, Op2, Op3; local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h23 SDValue Chain, SDValue Op1, SDValue Op2,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp142 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
148 Ops[5].getAsInteger(10, Op2);
149 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
160 uint32_t Op2 = Bits & 0x7; local
163 utostr(CRm) + "_" + utostr(Op2);
/netbsd-current/sys/external/bsd/acpica/dist/compiler/
H A Dasltree.c532 * Op2 - Second peer
543 ACPI_PARSE_OBJECT *Op2)
551 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL);
554 if ((!Op1) && (!Op2))
562 if (!Op2)
569 return (Op2);
572 if (Op1 == Op2)
582 Op1->Asl.Parent = Op2
541 TrLinkPeerOp( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument
678 TrLinkChildOp( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp283 const MachineMemOperand &Op2,
285 if (!Op1.getValue() || !Op2.getValue())
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset());
290 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset;
295 MemoryLocation(Op2.getValue(), Overlapb,
296 UseTBAA ? Op2.getAAInfo() : AAMDNodes()));
308 for (const MachineMemOperand *Op2 : MI2.memoperands())
309 if (alias(*Op1, *Op2, UseTBAA))
282 alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2, bool UseTBAA) const argument
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { argument
171 if (Op1.getType() != Op2.getType())
176 return Op1.getReg() == Op2.getReg();
178 return Op1.getImm() == Op2.getImm();
294 MachineOperand &Op2 = AluIter->getOperand(2); local
301 if (Op2.isImm()) {
312 // Check that the Op2 would fit in the immediate field of the
314 ((IsSpls && isInt<10>(Op2.getImm())) ||
315 (!IsSpls && isInt<16>(Op2.getImm())))) ||
316 Offset.getImm() == Op2
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3,
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile,
82 SDValue Op2, SDValue Op3,
94 SDValue Op1, SDValue Op2, SDValue Op3,
131 SDValue Op1, SDValue Op2,
51 EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
67 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
80 EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
93 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
130 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp108 MachineOperand &Op2 = A->getOperand(2); local
109 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
115 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0))
120 if (Op2.isReg()) {
121 SReg = Op2.getReg();
137 if (!ReadsSreg && Op2.isKill()) {
141 } else if (Op2
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H A DSIOptimizeExecMaskingPreRA.cpp156 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); local
157 if (Op1->isImm() && Op2->isReg())
158 std::swap(Op1, Op2);
159 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
172 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);
174 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
175 Op1->getImm() != 0 || Op2->getImm() != 1)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp270 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; local
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
274 && (Op2.getToken() == "-" || Op2.getToken() == "be16"
275 || Op2.getToken() == "be32" || Op2.getToken() == "be64"
276 || Op2.getToken() == "le16" || Op2.getToken() == "le32"
277 || Op2.getToken() == "le64")
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp153 const MCOperand &Op2 = MI->getOperand(opNum + 1); local
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) ||
165 (Op2.isImm() && Op2.getImm() == 0));
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp71 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); local
72 if (!Op1.isReg() || !Op2.isReg())
75 return Op1.getReg() == Op2.getReg();
H A DPPCBranchCoalescing.cpp342 const MachineOperand &Op2 = OpList2[i]; local
345 << "Op2: " << Op2 << "\n"); local
347 if (Op1.isIdenticalTo(Op2)) {
357 LLVM_DEBUG(dbgs() << "Op1 and Op2 are identical!\n");
364 if (Op1.isReg() && Op2.isReg() &&
366 Register::isVirtualRegister(Op2.getReg())) {
368 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg());
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h56 SDValue Chain, SDValue Op1, SDValue Op2,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
330 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) {
331 assert((Op1 || Op2) && "Nothing to check");
336 if (Op1 && Op2)
337 OrV = Builder.CreateOr(Op1, Op2);
339 OrV = Op1 ? Op1 : Op2;
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/
H A DDWARFExpression.h72 Encoding Op2 = SizeNA)
75 Op[1] = Op2;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp345 const MachineOperand &Op2 = MI->getOperand(2); local
347 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0;
728 MachineOperand &Op2 = MI->getOperand(2); local
745 if (!Op2.isReg()) {
747 .add(Op2);
750 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
780 MachineOperand &Op2 local
904 MachineOperand &Op2 = MI->getOperand(2); local
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