/netbsd-current/external/gpl3/gdb/dist/opcodes/ |
H A D | aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} macro 2761 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2763 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2767 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2770 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2773 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), 2775 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2778 CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2784 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 2786 CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (R [all...] |
H A D | cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ 144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} 150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
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/netbsd-current/external/gpl3/binutils/dist/opcodes/ |
H A D | aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} macro 2955 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2957 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2961 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2964 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2967 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), 2969 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2972 CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2978 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 2980 CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (R [all...] |
H A D | cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ 144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} 150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
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/netbsd-current/external/gpl3/binutils.old/dist/opcodes/ |
H A D | aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} macro 2747 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2749 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2753 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2756 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2759 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), 2761 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2764 CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2770 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 2772 CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (R [all...] |
H A D | cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ 144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} 150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
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/netbsd-current/external/gpl3/gdb.old/dist/opcodes/ |
H A D | aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} macro 2571 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2573 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 2577 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2580 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 2583 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), 2585 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2588 CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 2594 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 2596 CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (R [all...] |
H A D | cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ 144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} 150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ 152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ 154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
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/netbsd-current/external/cddl/osnet/dist/lib/libdtrace/common/ |
H A D | dt_grammar.y | 35 #define OP2(op, l, r) dt_node_op2(op, l, r) 405 $$ = OP2(DT_TOK_LBRAC, $1, $3); 415 $$ = OP2(DT_TOK_DOT, $1, dt_node_ident($3)); 418 $$ = OP2(DT_TOK_DOT, $1, dt_node_ident($3)); 421 $$ = OP2(DT_TOK_DOT, $1, dt_node_ident($3)); 424 $$ = OP2(DT_TOK_PTR, $1, dt_node_ident($3)); 427 $$ = OP2(DT_TOK_PTR, $1, dt_node_ident($3)); 430 $$ = OP2(DT_TOK_PTR, $1, dt_node_ident($3)); 452 $$ = OP2(DT_TOK_XLATE, dt_node_type($3), $6); 481 $$ = OP2(DT_TOK_LPA [all...] |
/netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/cast/ |
H A D | cast_local.h | 130 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \ 137 CAST_S_table0+((t>>C_2)&C_M)) OP2 \ 146 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \ 159 t=(t OP2 *(CAST_LONG *)((unsigned char *)CAST_S_table1+v))&0xffffffffL;\ 168 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \ 177 L^=(((((a OP2 b)&0xffffffffL) OP3 c)&0xffffffffL) OP1 d)&0xffffffffL; \
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/netbsd-current/crypto/external/bsd/openssl/dist/crypto/cast/ |
H A D | cast_local.h | 130 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \ 137 CAST_S_table0+((t>>C_2)&C_M)) OP2 \ 146 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \ 159 t=(t OP2 *(CAST_LONG *)((unsigned char *)CAST_S_table1+v))&0xffffffffL;\ 168 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \ 177 L^=(((((a OP2 b)&0xffffffffL) OP3 c)&0xffffffffL) OP1 d)&0xffffffffL; \
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/netbsd-current/external/gpl3/binutils/dist/include/opcode/ |
H A D | tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } macro 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG 3597 #undef OP2 macro [all...] |
H A D | h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \ 558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ 562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} 564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \ 576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/include/opcode/ |
H A D | tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } macro 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG 3597 #undef OP2 macro [all...] |
H A D | h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \ 558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ 562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} 564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \ 576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, [all...] |
/netbsd-current/external/gpl3/gdb/dist/include/opcode/ |
H A D | tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } macro 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG 3597 #undef OP2 macro [all...] |
H A D | h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \ 558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ 562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} 564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \ 576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, [all...] |
/netbsd-current/external/gpl3/binutils.old/dist/include/opcode/ |
H A D | tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } macro 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG 3597 #undef OP2 macro [all...] |
H A D | h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \ 558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ 561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ 562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} 564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ 572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \ 576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, [all...] |
/netbsd-current/external/gpl3/gcc.old/dist/libgcc/config/msp430/ |
H A D | lib2hw_mul.S | 93 .macro mult16 OP1, OP2, RESULT 108 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY 112 .macro mult1632 OP1, OP2, RESLO, RESHI 129 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY 134 .macro mult32 OP1, OP2, MAC_OP1, MAC_OP2, RESLO, RESHI 150 MOV.W r14, &\OP2 ; Load operand 2 Low which triggers MPY 278 .set OP2, 0x0138 320 mult16 MPY, OP2, RESLO 324 mult1632 MPYS, OP2, RESLO, RESHI 328 mult1632 MPY, OP2, RESL [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600Defines.h | 39 OP2 = (1 << 11), enumerator in enum:R600_InstFlag::TIF
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/netbsd-current/external/gpl3/gcc/dist/libgcc/config/msp430/ |
H A D | lib2hw_mul.S | 93 .macro mult16 OP1, OP2, RESULT 108 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY 112 .macro mult1632 OP1, OP2, RESLO, RESHI 129 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY 134 .macro mult32 OP1, OP2, MAC_OP1, MAC_OP2, RESLO, RESHI 150 MOV.W r14, &\OP2 ; Load operand 2 Low which triggers MPY 345 .set OP2, 0x0138 387 mult16 MPY, OP2, RESLO 391 mult1632 MPYS, OP2, RESLO, RESHI 395 mult1632 MPY, OP2, RESL [all...] |
/netbsd-current/external/gpl3/gcc.old/dist/libgcc/config/mips/ |
H A D | mips16.S | 105 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */ 106 #define DELAYt(T, OPCODE, OP2) \ 109 OPCODE, OP2; \ 114 #define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2) 116 /* Use "OPCODE. OP2" and jump to T. */ 117 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
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/netbsd-current/external/gpl3/gcc/dist/libgcc/config/mips/ |
H A D | mips16.S | 105 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */ 106 #define DELAYt(T, OPCODE, OP2) \ 109 OPCODE, OP2; \ 114 #define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2) 116 /* Use "OPCODE. OP2" and jump to T. */ 117 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
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/netbsd-current/external/cddl/osnet/dist/lib/libdtrace/sparc/ |
H A D | dt_isadep.c | 39 #define OP2(x) (((x) >> 22) & 0x07) macro 196 switch (OP2(text[i])) {
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