Searched refs:MULHU (Results 1 - 25 of 40) sorted by relevance

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/netbsd-current/external/gpl3/binutils/dist/gas/config/
H A Drl78-parse.h134 MULHU = 335, /* MULHU */ enumerator in enum:yytokentype
259 #define MULHU 335 macro
H A Drl78-parse.y173 %token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
507 | MULHU { ISA_G14 ("MULHU"); }
1304 OPC(MULHU),
H A Drl78-parse.c320 MULHU = 335, /* MULHU */ enumerator in enum:yytokentype
445 #define MULHU 335 macro
595 YYSYMBOL_MULHU = 80, /* MULHU */
1154 "MULHU", "MULU", "NOP", "NOT1", "ONEB", "ONEW", "OR", "OR1", "POP",
2751 { ISA_G14 ("MULHU"); }
2755 case 93: /* statement: MULHU $@12 */
4548 OPC(MULHU),
/netbsd-current/external/gpl3/binutils.old/dist/gas/config/
H A Drl78-parse.h134 MULHU = 335, /* MULHU */ enumerator in enum:yytokentype
259 #define MULHU 335 macro
H A Drl78-parse.y173 %token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
507 | MULHU { ISA_G14 ("MULHU"); }
1304 OPC(MULHU),
H A Drl78-parse.c320 MULHU = 335, /* MULHU */ enumerator in enum:yytokentype
445 #define MULHU 335 macro
595 YYSYMBOL_MULHU = 80, /* MULHU */
1154 "MULHU", "MULU", "NOP", "NOT1", "ONEB", "ONEW", "OR", "OR1", "POP",
2751 { ISA_G14 ("MULHU"); }
2755 case 93: /* statement: MULHU $@12 */
4548 OPC(MULHU),
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMips16ISelDAGToDAG.cpp211 case ISD::MULHU: {
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
H A DMipsSEISelLowering.cpp186 setOperationAction(ISD::MULHU, MVT::i32, Custom);
197 setOperationAction(ISD::MULHU, MVT::i64, Custom);
234 setOperationAction(ISD::MULHU, MVT::i32, Legal);
281 setOperationAction(ISD::MULHU, MVT::i64, Legal);
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h608 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
611 MULHU, enumerator in enum:llvm::ISD::NodeType
/netbsd-current/external/gpl3/gdb.old/dist/gas/config/
H A Drl78-parse.y173 %token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
507 | MULHU { ISA_G14 ("MULHU"); }
1304 OPC(MULHU),
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp392 setOperationAction(ISD::MULHU, MVT::i16, Expand);
396 setOperationAction(ISD::MULHU, MVT::i64, Expand);
425 setOperationAction(ISD::MULHU, VT, Expand);
554 setTargetDAGCombine(ISD::MULHU);
1840 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1855 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1869 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
2011 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ));
2014 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z);
3983 case ISD::MULHU
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h387 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
838 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1058 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp111 setOperationAction(ISD::MULHU, MVT::i32, Legal);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp107 setOperationAction(ISD::MULHU, VT, Expand);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp117 setOperationAction(ISD::MULHU, T, Custom);
179 setOperationAction(ISD::MULHU, T, Custom);
2076 case ISD::MULHU:
2116 case ISD::MULHU: return LowerHvxMulh(Op, DAG);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp232 case ISD::MULHU: return "mulhu";
H A DLegalizeDAG.cpp3270 case ISD::MULHU:
3273 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3288 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3326 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
H A DLegalizeVectorOps.cpp367 case ISD::MULHU:
H A DTargetLowering.cpp5360 if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization))
5361 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
5382 // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
6265 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
6291 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
8135 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
8406 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp123 setOperationAction(ISD::MULHU, MVT::i8, Promote);
128 setOperationAction(ISD::MULHU, MVT::i16, Expand);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp114 setOperationAction(ISD::MULHU, MVT::i32, Expand);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp179 setOperationAction(ISD::MULHU, VT, Expand);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1010 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp100 setOperationAction(ISD::MULHU, MVT::i32, Expand);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1657 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1680 setOperationAction(ISD::MULHU, MVT::i64, Expand);

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