Searched refs:MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h18814 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT macro
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H A Ddcn_2_1_0_sh_mask.h20190 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT macro
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H A Ddcn_2_0_0_sh_mask.h23258 #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT macro
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