Searched refs:MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_0_0_sh_mask.h3647 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 macro
H A Dmmhub_9_4_1_sh_mask.h10714 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT macro
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