Searched refs:MIPS_INT_MASK (Results 1 - 25 of 47) sorted by relevance

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/netbsd-current/sys/arch/arc/arc/
H A Dp_sni_rm200pci.c95 [IPL_VM] = MIPS_INT_MASK, /* XXX */
96 [IPL_SCHED] = MIPS_INT_MASK,
97 [IPL_DDB] = MIPS_INT_MASK,
98 [IPL_HIGH] = MIPS_INT_MASK,
H A Dp_dti_tyne.c114 [IPL_VM] = MIPS_INT_MASK, /* XXX */
115 [IPL_SCHED] = MIPS_INT_MASK,
116 [IPL_DDB] = MIPS_INT_MASK,
117 [IPL_HIGH] = MIPS_INT_MASK,
H A Dp_dti_arcstation.c111 [IPL_VM] = MIPS_INT_MASK, /* XXX */
112 [IPL_SCHED] = MIPS_INT_MASK,
113 [IPL_DDB] = MIPS_INT_MASK,
114 [IPL_HIGH] = MIPS_INT_MASK,
H A Dc_magnum.c99 [IPL_SCHED] = MIPS_INT_MASK,
100 [IPL_DDB] = MIPS_INT_MASK,
101 [IPL_HIGH] = MIPS_INT_MASK,
H A Dc_nec_eisa.c120 [IPL_SCHED] = MIPS_INT_MASK,
121 [IPL_DDB] = MIPS_INT_MASK,
122 [IPL_HIGH] = MIPS_INT_MASK,
H A Dc_nec_pci.c125 [IPL_SCHED] = MIPS_INT_MASK,
126 [IPL_DDB] = MIPS_INT_MASK,
127 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/mips/include/
H A Dpsl.h69 #define MIPS1_PSL_LOWIPL (MIPS_INT_MASK | MIPS_SR_INT_IE)
76 MIPS_INT_MASK)
/netbsd-current/sys/arch/hpcmips/vr/
H A Dvrip_spl.S65 li v1, ~MIPS_INT_MASK
/netbsd-current/sys/arch/mipsco/mipsco/
H A Dinterrupt.c65 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/emips/include/
H A Dintr.h49 #define MIPS_SPLHIGH (MIPS_INT_MASK)
/netbsd-current/sys/arch/pmax/include/
H A Dintr.h44 #define MIPS_SPLHIGH (MIPS_INT_MASK)
/netbsd-current/sys/arch/algor/algor/
H A Dalgor_intr.c80 [IPL_SCHED] = MIPS_INT_MASK,
81 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/mips/mips/
H A Dspl.S53 .word MIPS_INT_MASK /* IPL_VM */
54 .word MIPS_INT_MASK /* IPL_SCHED */
55 .word MIPS_INT_MASK /* IPL_DDB */
56 .word MIPS_INT_MASK /* IPL_HIGH */
80 or v1, MIPS_INT_MASK # enable all interrupts
137 xor a1, MIPS_INT_MASK # invert SR bits
163 and v1, MIPS_INT_MASK
164 xor a1, MIPS_INT_MASK
176 xor v1, MIPS_INT_MASK # invert
260 and a0, v1, MIPS_INT_MASK # selec
[all...]
H A Dmips_machdep.c2146 | (ipl_sr_map.sr_bits[IPL_SCHED] ^ MIPS_INT_MASK);
2379 status = mips_cp0_status_read() & MIPS_INT_MASK;
2380 KASSERT(status == MIPS_INT_MASK);
2384 status = mips_cp0_status_read() & MIPS_INT_MASK;
2385 KASSERT((status ^ sr_map[IPL_SOFTCLOCK]) == MIPS_INT_MASK);
2390 status = mips_cp0_status_read() & MIPS_INT_MASK;
2391 KASSERT((status ^ sr_map[IPL_SOFTBIO]) == MIPS_INT_MASK);
2396 status = mips_cp0_status_read() & MIPS_INT_MASK;
2397 KASSERT((status ^ sr_map[IPL_SOFTNET]) == MIPS_INT_MASK);
2402 status = mips_cp0_status_read() & MIPS_INT_MASK;
[all...]
/netbsd-current/sys/arch/evbmips/mipssim/
H A Dmipssim_intr.c58 [IPL_DDB] = MIPS_INT_MASK,
59 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/ews4800mips/ews4800mips/
H A Dtr2a_intr.c56 [IPL_VM] = MIPS_INT_MASK & ~MIPS_INT_MASK_5,
57 [IPL_SCHED] = MIPS_INT_MASK,
58 [IPL_DDB] = MIPS_INT_MASK,
59 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/emips/emips/
H A Dxs_bee3.c60 #define NOINTS MIPS_INT_MASK
H A Dxilinx_ml40x.c62 #define NOINTS MIPS_INT_MASK
/netbsd-current/sys/arch/mips/ralink/
H A Dralink_intr.c61 [IPL_VM] = MIPS_INT_MASK ^ MIPS_INT_MASK_5,
62 [IPL_SCHED] = MIPS_INT_MASK,
63 [IPL_DDB] = MIPS_INT_MASK,
64 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/mips/adm5120/
H A Dadm5120_intr.c98 [IPL_SCHED] = MIPS_INT_MASK,
99 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/newsmips/newsmips/
H A Dnews5000.c73 [IPL_DDB] = MIPS_INT_MASK,
74 [IPL_HIGH] = MIPS_INT_MASK,
H A Dnews4000.c68 [IPL_DDB] = MIPS_INT_MASK,
69 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/cobalt/cobalt/
H A Dinterrupt.c149 [IPL_VM] = MIPS_INT_MASK ^ MIPS_INT_MASK_5,
150 [IPL_SCHED] = MIPS_INT_MASK,
151 [IPL_DDB] = MIPS_INT_MASK,
152 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/pmax/pmax/
H A Ddec_maxine.c127 [IPL_SCHED] = MIPS_INT_MASK,
128 [IPL_DDB] = MIPS_INT_MASK,
129 [IPL_HIGH] = MIPS_INT_MASK,
/netbsd-current/sys/arch/mips/atheros/
H A Dar5312.c380 [IPL_SCHED] = MIPS_INT_MASK,
381 [IPL_DDB] = MIPS_INT_MASK,
382 [IPL_HIGH] = MIPS_INT_MASK,

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