Searched refs:MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h9034 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc macro
H A Dgmc_6_0_sh_mask.h9591 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0x0000000c macro
H A Dgmc_8_1_sh_mask.h9946 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc macro

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