Searched refs:MASTER_COMM_CNTL_REG (Results 1 - 5 of 5) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_dmcu.c | 140 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
153 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
234 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
276 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
311 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
322 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
365 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
375 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
378 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
401 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUP
[all...] |
| H A D | amdgpu_dce_abm.c | 71 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
83 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
85 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
224 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
239 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
252 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
325 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
334 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
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| H A D | dce_dmcu.h | 44 SR(MASTER_COMM_CNTL_REG), \
61 SR(MASTER_COMM_CNTL_REG), \
98 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
124 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
178 uint32_t MASTER_COMM_CNTL_REG; member in struct:dce_dmcu_registers
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| H A D | dce_abm.h | 40 SR(MASTER_COMM_CNTL_REG), \
99 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
220 uint32_t MASTER_COMM_CNTL_REG; member in struct:dce_abm_registers
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| H A D | dce_link_encoder.h | 124 uint32_t MASTER_COMM_CNTL_REG; member in struct:dce110_link_enc_registers
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