Searched refs:MAL0_CFG_SR (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/arch/powerpc/ibm4xx/dev/
H A Dmal.c84 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR);
86 while (mfdcr(DCR_MAL0_CFG) & MAL0_CFG_SR) {
/netbsd-current/sys/arch/powerpc/include/ibm4xx/
H A Ddcr4xx.h131 #define MAL0_CFG_SR 0x80000000 /* Software Reset */ macro

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