Searched refs:LRU (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineOutliner.h73 LiveRegUnits LRU; member in struct:llvm::outliner::Candidate
146 LRU.init(TRI);
147 LRU.addLiveOuts(*MBB);
152 [this](MachineInstr &MI) { LRU.stepBackward(MI); });
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp124 LiveRegUnits LRU(*MBB.getParent()->getSubtarget().getRegisterInfo());
125 LRU.addLiveOuts(MBB);
126 bool NZCVDead = LRU.available(AArch64::NZCV);
129 LRU.stepBackward(II);
140 bool NZCVDeadAtCurrInstr = LRU.available(AArch64::NZCV);
/netbsd-current/lib/libc/db/hash/
H A Dhash_buf.c89 #define LRU hashp->bufhead.prev macro
92 #define LRU_INSERT(B) BUF_INSERT((B), LRU)
168 bp = LRU;
170 * If LRU buffer is pinned, the buffer pool is too small. We need to
305 if (!LRU)
307 for (bp = LRU; bp != &hashp->bufhead;) {
323 bp = LRU;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp744 LiveRegUnit &LRU = RegUnits[*Units];
745 LRU.MI = UseMI;
746 LRU.Op = DefOp;
936 LiveRegUnit &LRU = RegUnits[*Units];
938 if (LRU.Cycle <= Height && LRU.MI != &MI) {
939 LRU.Cycle = Height;
940 LRU.MI = &MI;
941 LRU.Op = ReadOps[I];
H A DEarlyIfConversion.cpp413 for (unsigned LRU : LiveRegUnits)
414 dbgs() << ' ' << printRegUnit(LRU, TRI);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp5705 assert(C.LRUWasSet && "LRU wasn't set?");
5717 C.LRU.available(Reg) && C.UsedInSequence.available(Reg))
5792 LiveRegUnits LRU = C.LRU;
5793 return (!LRU.available(ARM::R12) || !LRU.available(ARM::CPSR));
5854 : C.LRU.available(ARM::LR);
6055 LiveRegUnits LRU(getRegisterInfo());
6058 [&LRU](MachineInstr &MI) { LRU
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp6343 assert(C.LRUWasSet && "LRU wasn't set?");
6355 C.LRU.available(Reg) && C.UsedInSequence.available(Reg))
6528 LiveRegUnits LRU = C.LRU;
6529 return (!LRU.available(AArch64::W16) || !LRU.available(AArch64::W17) ||
6530 !LRU.available(AArch64::NZCV));
6692 if (C.LRU.available(AArch64::LR) && !IsNoReturn) {
6781 (!C.LRU.available(AArch64::LR) || !findRegisterToSaveLRTo(C));
6869 LiveRegUnits LRU(getRegisterInf
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp1013 LiveRegUnits LRU = C.LRU;
1014 return !LRU.available(RISCV::X5);

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