Searched refs:IMMU (Results 1 - 9 of 9) sorted by relevance

/netbsd-current/external/gpl3/binutils/dist/opcodes/
H A Drl78-decode.c77 #define IMMU(bytes) immediate (bytes, 0, ld) macro
168 #define SADDR saddr (IMMU (1))
169 #define SFR sfr (IMMU (1))
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
312 ID(mov); DR(A); SM(B, IMMU(2));
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
389 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
404 ID(add); DR(A); SM(None, IMMU(
[all...]
H A Dmsp430-decode.c100 #define IMMU(bytes) immediate (bytes, 0, ld) macro
173 int x = IMMU(2) | (ext << 16);
216 x = IMMU(2) | (ext << 16);
220 x = IMMU(2) | (ext << 16);
227 x = IMMU(2) | (ext << 16);
255 x = IMMU(2) | (ext << 16);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
504 ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(
[all...]
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/
H A Drl78-decode.c77 #define IMMU(bytes) immediate (bytes, 0, ld) macro
168 #define SADDR saddr (IMMU (1))
169 #define SFR sfr (IMMU (1))
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
312 ID(mov); DR(A); SM(B, IMMU(2));
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
389 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
404 ID(add); DR(A); SM(None, IMMU(
[all...]
H A Dmsp430-decode.c100 #define IMMU(bytes) immediate (bytes, 0, ld) macro
173 int x = IMMU(2) | (ext << 16);
216 x = IMMU(2) | (ext << 16);
220 x = IMMU(2) | (ext << 16);
227 x = IMMU(2) | (ext << 16);
255 x = IMMU(2) | (ext << 16);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
504 ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/
H A Drl78-decode.c77 #define IMMU(bytes) immediate (bytes, 0, ld) macro
168 #define SADDR saddr (IMMU (1))
169 #define SFR sfr (IMMU (1))
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
312 ID(mov); DR(A); SM(B, IMMU(2));
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
389 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
404 ID(add); DR(A); SM(None, IMMU(
[all...]
H A Dmsp430-decode.c100 #define IMMU(bytes) immediate (bytes, 0, ld) macro
173 int x = IMMU(2) | (ext << 16);
216 x = IMMU(2) | (ext << 16);
220 x = IMMU(2) | (ext << 16);
227 x = IMMU(2) | (ext << 16);
255 x = IMMU(2) | (ext << 16);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
504 ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(
[all...]
/netbsd-current/external/gpl3/gdb/dist/opcodes/
H A Drl78-decode.c77 #define IMMU(bytes) immediate (bytes, 0, ld) macro
168 #define SADDR saddr (IMMU (1))
169 #define SFR sfr (IMMU (1))
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
312 ID(mov); DR(A); SM(B, IMMU(2));
327 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac;
389 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
404 ID(add); DR(A); SM(None, IMMU(
[all...]
H A Dmsp430-decode.c100 #define IMMU(bytes) immediate (bytes, 0, ld) macro
173 int x = IMMU(2) | (ext << 16);
216 x = IMMU(2) | (ext << 16);
220 x = IMMU(2) | (ext << 16);
227 x = IMMU(2) | (ext << 16);
255 x = IMMU(2) | (ext << 16);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
504 ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(
[all...]
/netbsd-current/sys/arch/sparc64/sparc64/
H A Dlocore.s713 ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
717 ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
924 ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
928 ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
5966 * Flush tte from both IMMU and DMMU.
6061 !! Cheetahs do not support flushing the IMMU from secondary context
6101 * Flush all user TLB entries from both IMMU and DMMU.
6141 * now do the IMMU

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