Searched refs:HCLR4 (Results 1 - 25 of 74) sorted by relevance

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/openbsd-current/sys/dev/fdt/
H A Dmviic.c90 #define HCLR4(sc, reg, bits) \ macro
141 HCLR4(sc, ICR, ICR_RESET);
237 HCLR4(sc, ICR, ICR_START);
238 HCLR4(sc, ICR, ICR_STOP);
263 HCLR4(sc, ICR, ICR_START);
264 HCLR4(sc, ICR, ICR_STOP);
265 HCLR4(sc, ICR, ICR_NAK);
285 HCLR4(sc, ICR, ICR_START);
286 HCLR4(sc, ICR, ICR_STOP);
306 HCLR4(s
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H A Dmvdog.c42 #define HCLR4(sc, reg, bits) \ macro
99 HCLR4(sc, CNTR_CTRL(CNTR_WDOG), CNTR_CTRL_ENABLE);
100 HCLR4(sc, CNTR_CTRL(CNTR_RETRIGGER), CNTR_CTRL_ENABLE);
H A Dsxirintc.c38 #define HCLR4(sc, reg, bits) \ macro
108 HCLR4(sc, RINTC_IRQ_ENABLE, RINTC_IRQ_ENABLE_NMI);
H A Dmvgpio.c43 #define HCLR4(sc, reg, bits) \ macro
110 HCLR4(sc, GPIO_DOUTEN, (1 << pin));
151 HCLR4(sc, GPIO_DOUT, (1 << pin));
H A Damlreset.c41 #define HCLR4(sc, reg, bits) \ macro
107 HCLR4(sc, RESET0_LEVEL + bank * 4, (1 << bit));
H A Ddwdog.c47 #define HCLR4(sc, reg, bits) \ macro
110 HCLR4(sc, WDT_CR, WDT_CR_RESP_MODE | WDT_CR_WDT_EN);
H A Drkpwm.c50 #define HCLR4(sc, reg, bits) \ macro
157 HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_ENABLE | PWM_V2_CTRL_CONTINUOUS);
171 HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_INACTIVE_POSITIVE);
172 HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_DUTY_POSITIVE);
H A Drkgpio.c76 #define HCLR4(sc, reg, bits) \ macro
222 HCLR4(sc, GPIO_SWPORTA_DDR, (1 << pin));
270 HCLR4(sc, GPIO_SWPORTA_DR, (1 << pin));
392 HCLR4(sc, GPIO_INT_POLARITY, 1 << irqno);
395 HCLR4(sc, GPIO_INTTYPE_LEVEL, 1 << irqno);
399 HCLR4(sc, GPIO_INTTYPE_LEVEL, 1 << irqno);
400 HCLR4(sc, GPIO_INT_POLARITY, 1 << irqno);
406 HCLR4(sc, GPIO_SWPORTA_DDR, 1 << irqno);
407 HCLR4(sc, GPIO_INTMASK, 1 << irqno);
495 HCLR4(s
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H A Dmvspi.c87 #define HCLR4(sc, reg, bits) \ macro
146 HCLR4(sc, SPI_CFG, SPI_CFG_FIFO_ENABLE);
147 HCLR4(sc, SPI_CFG, SPI_CFG_BYTE_LEN);
183 HCLR4(sc, SPI_CFG, SPI_CFG_PRESCALE_MASK);
230 HCLR4(sc, SPI_CTRL, SPI_CTRL_CS(cs));
H A Drkspi.c124 #define HCLR4(sc, reg, bits) \ macro
278 HCLR4(sc, SPI_CTRLR0, SPI_CTRLR0_XFM_RO);
314 HCLR4(sc, SPI_SER, SPI_SER_CS(sc->sc_cs));
320 HCLR4(sc, SPI_SER, SPI_SER_CS(sc->sc_cs));
H A Dqcgpio_fdt.c54 #define HCLR4(sc, reg, bits) \ macro
172 HCLR4(sc, TLMM_GPIO_CFG(pin), TLMM_GPIO_CFG_OUT_EN);
211 HCLR4(sc, TLMM_GPIO_IN_OUT(pin),
302 HCLR4(sc, TLMM_GPIO_INTR_CFG(pin),
H A Dimxesdhc.c226 #define HCLR4(sc, reg, bits) \ macro
600 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK);
603 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DTW_MASK);
711 HCLR4(sc, SDHC_VEND_SPEC, SDHC_VEND_SPEC_FRC_SDCLK_ON);
718 HCLR4(sc, SDHC_SYS_CTRL, SDHC_SYS_CTRL_CLOCK_MASK);
766 HCLR4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT);
767 HCLR4(sc, SDHC_INT_SIGNAL_EN, SDHC_INT_STATUS_CINT);
977 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK);
983 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK);
1119 HCLR4(s
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H A Dqcpdc.c43 #define HCLR4(sc, reg, bits) \ macro
132 HCLR4(sc, PDC_INTR_ENABLE(sc->sc_pr[i].pin_base + j),
221 HCLR4(sc, PDC_INTR_ENABLE(ih->ih_pin), PDC_INTR_ENABLE_BIT(ih->ih_pin));
H A Damlclock.c112 #define HCLR4(sc, reg, bits) \ macro
327 HCLR4(sc, offset, HHI_SYS_CPU_CLK_POSTMUX0);
358 HCLR4(sc, offset, HHI_SYS_CPU_CLK_POSTMUX1);
393 HCLR4(sc, offset, HHI_SYS_DPLL_EN);
405 HCLR4(sc, offset, HHI_SYS_DPLL_RESET);
610 HCLR4(sc, sc->sc_gates[idx].reg,
H A Dmvpinctrl.c46 #define HCLR4(sc, reg, bits) \ macro
291 HCLR4(sc, GPIO_DIRECTION, (1 << pin));
329 HCLR4(sc, GPIO_OUTPUT, (1 << pin));
/openbsd-current/sys/arch/armv7/marvell/
H A Dmvodog.c39 #define HCLR4(sc, ioh, reg, bits) \ macro
103 HCLR4(sc, sc->sc_rstout_ioh, 0, RSTOUT_ENABLE);
104 HCLR4(sc, sc->sc_reg_ioh, 0, WDT_ENABLE);
H A Dmvagc.c34 #define HCLR4(sc, reg, bits) \ macro
114 HCLR4(sc, 0, (1 << id));
H A Dmvsysctrl.c39 #define HCLR4(sc, reg, bits) \ macro
/openbsd-current/sys/arch/riscv64/dev/
H A Dsfgpio.c60 #define HCLR4(sc, reg, bits) \ macro
170 HCLR4(sc, GPIO_INPUT_EN, (1 << pin));
173 HCLR4(sc, GPIO_OUTPUT_EN, (1 << pin));
211 HCLR4(sc, GPIO_OUTPUT_VAL, (1 << pin));
339 HCLR4(sc, GPIO_RISE_IE, (1 << ih->ih_pin));
342 HCLR4(sc, GPIO_FALL_IE, (1 << ih->ih_pin));
345 HCLR4(sc, GPIO_HIGH_IE, (1 << ih->ih_pin));
348 HCLR4(sc, GPIO_LOW_IE, (1 << ih->ih_pin));
/openbsd-current/sys/dev/acpi/
H A Ddwgpio.c49 #define HCLR4(sc, reg, bits) \ macro
227 HCLR4(sc, GPIO_SWPORTA_DR, (1 << pin));
245 HCLR4(sc, GPIO_INTTYPE_LEVEL, 1 << pin);
249 HCLR4(sc, GPIO_INT_POLARITY, 1 << pin);
251 HCLR4(sc, GPIO_SWPORTA_DDR, 1 << pin);
253 HCLR4(sc, GPIO_INTMASK, 1 << pin);
/openbsd-current/sys/arch/armv7/exynos/
H A Dexpower.c37 #define HCLR4(sc, reg, bits) \ macro
H A Dexiic.c99 #define HCLR4(sc, reg, bits) \ macro
313 HCLR4(sc, I2C_CON, I2C_CON_ACK);
342 HCLR4(sc, I2C_CON, I2C_CON_INTPENDING);
/openbsd-current/sys/arch/armv7/imx/
H A Dimxtemp.c67 #define HCLR4(sc, reg, bits) \ macro
188 HCLR4(sc, TEMPMON_TEMPSENSE0, TEMPMON_TEMPSENSE0_POWER_DOWN);
205 HCLR4(sc, TEMPMON_TEMPSENSE0, TEMPMON_TEMPSENSE0_MEASURE_TEMP);
/openbsd-current/sys/arch/armv7/omap/
H A Dommmc.c227 #define HCLR4(sc, reg, bits) \ macro
549 HCLR4(sc, MMCHS_CON, MMCHS_CON_INIT);
569 HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8);
570 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);
631 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP);
734 HCLR4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN);
754 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE);
793 HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8);
798 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);
815 HCLR4(s
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/openbsd-current/sys/arch/arm64/dev/
H A Daplmca.c102 #define HCLR4(sc, reg, bits) \ macro
221 HCLR4(sc, MCA_SERDES_STATUS(i, MCA_SERDES_TXA),
223 HCLR4(sc, MCA_SYNCGEN_STATUS(i), MCA_SYNCGEN_STATUS_EN);
224 HCLR4(sc, MCA_STATUS(i), MCA_STATUS_MCLK_EN);
538 HCLR4(sc, MCA_SERDES_STATUS(ad->ad_cluster, MCA_SERDES_TXA),
540 HCLR4(sc, MCA_SYNCGEN_STATUS(ad->ad_cluster),
542 HCLR4(sc, MCA_STATUS(ad->ad_cluster), MCA_STATUS_MCLK_EN);

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