Searched refs:GICR_ISENABLER0 (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/arch/arm/cortex/
H A Dgic_reg.h212 #define GICR_ISENABLER0 0x10100 // Interrupt Set-Enable Register 0 macro
H A Dgicv3.c141 gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask);
331 gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, sc->sc_enabled_sgippi);

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