Searched refs:Def1 (Results 1 - 5 of 5) sorted by relevance
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenMux.cpp | 110 MachineInstr *Def1, *Def2; member in struct:__anon2418::HexagonGenMux::MuxInfo 115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), 304 MachineInstr &Def1 = *It1, &Def2 = *It2; local 305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); 327 MachineBasicBlock::iterator At = CanDown ? Def2 : Def1; 328 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); 336 // iterators. There is a possibility that one of Def1 or Def2 is translated 338 if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent()) 348 B.remove(MX.Def1);
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H A D | HexagonEarlyIfConv.cpp | 480 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); local 482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3))
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCReduceCRLogicals.cpp | 472 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(), local 474 assert(Def1 && "Must be able to find a definition of operand 1."); 476 MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg()); 489 Ret.TrueDefs = std::make_pair(Def1, Def2); 491 Ret.TrueDefs = std::make_pair(Def1, nullptr); 645 if (Def1It == Def2It) { // Def2 comes before Def1.
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1896 MachineInstr *Def1 = MRI->getVRegDef(Addr1); local 1899 if (!produceSameValue(*Def0, *Def1, MRI))
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 5116 bool Def1 = !Elems[I1].isUndef(); 5118 if (Def1 || Def2) { 5119 SDValue Elem1 = Elems[Def1 ? I1 : I2];
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