Searched refs:DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_sh_mask.h47259 #define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT macro
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H A Ddcn_2_0_0_sh_mask.h53826 #define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT macro
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