Searched refs:DRAMClockChangeSupport (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
H A Damdgpu_display_mode_vba_21.c339 enum clock_change_support *DRAMClockChangeSupport,
2415 enum clock_change_support DRAMClockChangeSupport; // dummy local
2465 &DRAMClockChangeSupport,
5022 &locals->DRAMClockChangeSupport[i][j],
5189 && ((locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
5190 && locals->DRAMClockChangeSupport[i][0] != dm_dram_clock_change_vactive)
5191 || (locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank
5192 && locals->DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported))))) {
5277 enum clock_change_support *DRAMClockChangeSupport,
5484 *DRAMClockChangeSupport
5228 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, double DETBufferSizeInKByte, unsigned int WritebackInterfaceLumaBufferSize, unsigned int WritebackInterfaceChromaBufferSize, double DCFCLK, double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], unsigned int SwathHeightY[], double ReadBandwidthPlaneLuma[], unsigned int SwathHeightC[], double ReadBandwidthPlaneChroma[], unsigned int LBBitPerPixel[], double SwathWidthY[], double HRatio[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h603 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES + 1][2]; member in struct:vba_vars_st
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
H A Damdgpu_display_mode_vba_20v2.c2623 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
2626 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
2629 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;
2632 mode_lib->vba.DRAMClockChangeSupport[0][0] =
2637 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported;
2642 mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
H A Damdgpu_display_mode_vba_20.c2589 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
2592 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;
2595 mode_lib->vba.DRAMClockChangeSupport[0][0] =
2600 mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported;
2605 mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_resource.c2794 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]

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