Searched refs:DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h3592 #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L macro
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H A Ddcn_2_1_0_sh_mask.h2093 #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L macro
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H A Ddcn_2_0_0_sh_mask.h2361 #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L macro
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