Searched refs:DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/df/
H A Ddf_3_6_sh_mask.h54 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_df_v3_6.c354 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;

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