Searched refs:DCR_MAL0_RXEOBISR (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/arch/powerpc/ibm4xx/dev/
H A Dmal.c160 while ((rcei = mfdcr(DCR_MAL0_RXEOBISR))) {
164 mtdcr(DCR_MAL0_RXEOBISR, MAL0__XCAR_CHAN(chan));
/netbsd-current/sys/arch/powerpc/include/ibm4xx/
H A Ddcr4xx.h207 #define DCR_MAL0_RXEOBISR 0x192 /* Rx End of Buffer Interrupt Status Register */ macro

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