Searched refs:DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h3418 #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 macro
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H A Ddce_11_2_sh_mask.h3672 #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 macro
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H A Ddce_10_0_sh_mask.h3340 #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 macro
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H A Ddce_12_0_sh_mask.h9504 #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 macro
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h40166 #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT macro
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