Searched refs:D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK (Results 1 - 10 of 10) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vi.c408 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h2525 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L macro
H A Ddce_8_0_sh_mask.h11037 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 macro
H A Ddce_11_0_sh_mask.h11233 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 macro
[all...]
H A Ddce_11_2_sh_mask.h12487 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 macro
[all...]
H A Ddce_10_0_sh_mask.h11421 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 macro
[all...]
H A Ddce_12_0_sh_mask.h2102 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L macro
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h1652 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L macro
[all...]
H A Ddcn_2_1_0_sh_mask.h153 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L macro
[all...]
H A Ddcn_2_0_0_sh_mask.h152 #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L macro
[all...]

Completed in 9207 milliseconds