Searched refs:CR_RST (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/arch/sandpoint/stand/altboot/
H A Dsip.c64 #define CR_RST (1U << 8) /* software reset */ macro
152 CSR_WRITE(l, SIP_CR, CR_RST);
155 } while (val & CR_RST); /* S1C */
/netbsd-current/sys/arch/mac68k/obio/
H A Dif_sn_obio.c204 CSR_WRITE(sc, SONIC_CR, CR_RST);
/netbsd-current/sys/dev/ic/
H A Ddp83932reg.h171 #define CR_RST (1U << 7) /* Software Reset */ macro
H A Ddp83932.c878 CSR_WRITE(sc, SONIC_CR, CR_RST);
921 CSR_WRITE(sc, SONIC_CR, CR_RST);
/netbsd-current/sys/arch/newsmips/apbus/
H A Dif_sn.c122 NIC_PUT(sc, SNR_CR, CR_RST);
376 NIC_PUT(sc, SNR_CR, CR_RST); /* DCR only accessible in reset mode! */
448 NIC_PUT(sc, SNR_CR, CR_RST);
700 NIC_PUT(sc, SNR_CR, CR_RST);
H A Dif_snreg.h89 * With the exception of CR_RST, the bit is reset when the operation
94 #define CR_RST 0x0080 /* software reset */ macro
105 * reset mode (s_cr.CR_RST is set.)
/netbsd-current/sys/dev/pci/
H A Dif_sipreg.h210 #define CR_RST 0x00000100 /* software reset */ macro
H A Dif_sip.c2528 bus_space_write_4(st, sh, SIP_CR, CR_RST);
2531 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0)

Completed in 282 milliseconds