Searched refs:CG_SCLK_DPM_CTRL_3 (Results 1 - 2 of 2) sorted by relevance
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_sumo_dpm.c | 544 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); 548 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); 606 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) 614 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); 619 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); 625 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); 627 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); 733 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); 947 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); 953 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_ [all...] |
H A D | sumod.h | 233 #define CG_SCLK_DPM_CTRL_3 0x6e0 macro
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