Searched refs:BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h647 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 macro
H A Dbif_5_1_sh_mask.h615 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 macro
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_sh_mask.h17686 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK macro
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H A Dnbio_7_0_sh_mask.h117962 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK macro
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