Searched refs:BASE_INNER (Results 1 - 24 of 24) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
H A Damdgpu_dmub_dcn21.c39 #define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg macro
H A Ddmub_reg.h37 #define BASE(seg) BASE_INNER(seg)
H A Damdgpu_dmub_dcn20.c40 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.h33 #define BASE_INNER(seg) \ macro
37 BASE_INNER(seg)
H A Ddcn20_dwb.h33 #define BASE_INNER(seg) \ macro
37 BASE_INNER(seg)
H A Ddcn20_mmhubbub.h35 #define BASE_INNER(seg) \ macro
39 BASE_INNER(seg)
H A Damdgpu_dcn20_resource.c378 #undef BASE_INNER macro
379 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
381 #define BASE(seg) BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
H A Damdgpu_hw_factory_dcn20.c57 #undef BASE_INNER macro
58 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
60 #define BASE(seg) BASE_INNER(seg)
H A Damdgpu_hw_translate_dcn20.c54 #undef BASE_INNER macro
55 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
57 #define BASE(seg) BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
H A Damdgpu_hw_factory_dcn21.c55 #undef BASE_INNER macro
56 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
58 #define BASE(seg) BASE_INNER(seg)
H A Damdgpu_hw_translate_dcn21.c54 #undef BASE_INNER macro
55 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
57 #define BASE(seg) BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
H A Damdgpu_hw_factory_dce120.c58 #define BASE_INNER(seg) \ macro
63 BASE_INNER(seg)
H A Damdgpu_hw_translate_dce120.c49 #define BASE_INNER(seg) \ macro
54 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
H A Damdgpu_hw_factory_dcn10.c55 #define BASE_INNER(seg) \ macro
60 BASE_INNER(seg)
H A Damdgpu_hw_translate_dcn10.c49 #define BASE_INNER(seg) \ macro
54 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
H A Damdgpu_irq_service_dcn20.c180 #undef BASE_INNER macro
181 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
185 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
H A Damdgpu_irq_service_dcn21.c176 #undef BASE_INNER macro
177 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
181 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
H A Damdgpu_irq_service_dce120.c99 #define BASE_INNER(seg) \ macro
103 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
H A Damdgpu_irq_service_dcn10.c180 #define BASE_INNER(seg) \ macro
184 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h32 #define BASE_INNER(seg) \ macro
36 BASE_INNER(seg)
H A Damdgpu_dcn10_resource.c170 #define BASE_INNER(seg) \ macro
174 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
H A Damdgpu_dcn20_clk_mgr.c53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
55 #define BASE(seg) BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_resource.c129 #define BASE_INNER(seg) \ macro
140 BASE_INNER(seg)
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_resource.c289 #undef BASE_INNER macro
290 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
292 #define BASE(seg) BASE_INNER(seg)

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