Searched refs:AR_CR (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/isc/atheros_hal/dist/ar5211/
H A Dar5211_recv.c55 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
64 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
65 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
68 "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n"
70 , OS_REG_READ(ah, AR_CR)
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */ macro
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5210/
H A Dar5210_recv.c54 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
65 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
67 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
73 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
H A Dar5210_xmit.c300 if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
301 ath_hal_printf(ah, "%s: TXE asserted; AR_CR=0x%x\n",
302 __func__, OS_REG_READ(ah, AR_CR));
378 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
381 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */
440 OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
446 OS_REG_WRITE(ah, AR_CR, 0);
H A Dar5210reg.h36 #define AR_CR 0x0008 /* Command register */ macro
/netbsd-current/sys/external/isc/atheros_hal/dist/ar5212/
H A Dar5212_recv.c53 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
62 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
63 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
66 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
68 OS_REG_READ(ah, AR_CR),
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */ macro
/netbsd-current/sys/dev/ic/
H A Dathnreg.h27 #define AR_CR 0x0008 macro
259 /* Bits for AR_CR. */
H A Dathn.c1780 AR_WRITE(sc, AR_CR, AR_CR_RXD);
1783 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
H A Darn5008.c720 AR_WRITE(sc, AR_CR, AR_CR_RXE);
955 AR_WRITE(sc, AR_CR, AR_CR_RXE);
H A Darn9003.c871 AR_WRITE(sc, AR_CR, 0);
1085 AR_WRITE(sc, AR_CR, 0);
/netbsd-current/sys/dev/usb/
H A Dif_athn_usb.c1733 AR_WRITE(sc, AR_CR, AR_CR_RXE);

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