Searched refs:RS (Results 1 - 25 of 96) sorted by relevance

1234

/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/include/opcode/
H A Di960.h85 * RS: global, local, or (if target allows) special-function register only
109 #define RS OP( 0, 0, 0, SFR ) macro
232 { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } },
233 { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } },
234 { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } },
235 { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } },
236 { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } },
237 { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } },
238 { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } },
239 { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS,
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/include/opcode/
H A Di960.h85 * RS: global, local, or (if target allows) special-function register only
109 #define RS OP( 0, 0, 0, SFR ) macro
232 { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } },
233 { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } },
234 { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } },
235 { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } },
236 { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } },
237 { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } },
238 { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } },
239 { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS,
[all...]
/netbsd-6-1-5-RELEASE/sys/arch/ia64/stand/efi/include/
H A Defilib.h34 extern EFI_RUNTIME_SERVICES *RS;
/netbsd-6-1-5-RELEASE/external/bsd/ntp/dist/include/
H A Dascii.h73 #define RS 30 macro
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/opcodes/
H A Diq2000-opc.c248 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
260 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
272 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
284 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
296 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
308 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
320 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
332 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
344 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
356 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', O
[all...]
H A Dxstormy16-opc.c214 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
220 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
226 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
232 { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
238 { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
244 { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
250 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
256 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
262 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
268 { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', O
[all...]
H A Dppc-opc.c398 the RS field in the instruction. This is used for extended
407 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
410 #define RS RBOPT + 1
411 #define RT RS
415 /* The RS and RT fields of the DS form stq instruction, which have
417 #define RSQ RS + 1
421 /* The RS field of the tlbwe instruction, which is optional. */
1210 the RS field in the instruction. This is used for extended
2166 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2168 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, R
408 #define RS macro
[all...]
H A Dh8500-opc.h145 #define RS 39 macro
199 {6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}},
200 {7,'-','X','!','!',O_XCH|O_UNSZ,"xch",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}},
474 {44,'-','B','S','S',O_SCB_NE|O_UNSZ,"scb/ne",2,{RS,PCREL8},3, {{0x06,0xff,0 },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}},
475 {45,'-','B','S','S',O_SCB_F|O_UNSZ,"scb/f",2,{RS,PCREL8},3, {{0x01,0xff,0 },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}},
476 {46,'-','B','S','S',O_SCB_EQ|O_UNSZ,"scb/eq",2,{RS,PCREL
[all...]
H A Di370-opc.c143 /* The R1 register field in an RX or RS form instruction. */
168 /* The D2 displacement field in an RS form instruction. */
171 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},
173 /* The R3 register field in an RS form instruction. */
176 { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },
178 /* The B2 base field in an RS form instruction. */
181 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},
183 /* The optional B2 base field in an RS form instruction. */
187 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},
365 /* An RS for
362 #define RS macro
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/opcodes/
H A Diq2000-opc.c248 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
260 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
272 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
284 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
296 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
308 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
320 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
332 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
344 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
356 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', O
[all...]
H A Dxstormy16-opc.c214 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
220 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
226 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
232 { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
238 { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
244 { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
250 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
256 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
262 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
268 { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', O
[all...]
H A Dppc-opc.c398 the RS field in the instruction. This is used for extended
407 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
410 #define RS RBOPT + 1
411 #define RT RS
415 /* The RS and RT fields of the DS form stq instruction, which have
417 #define RSQ RS + 1
421 /* The RS field of the tlbwe instruction, which is optional. */
1210 the RS field in the instruction. This is used for extended
2166 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}},
2168 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, R
408 #define RS macro
[all...]
H A Dh8500-opc.h145 #define RS 39 macro
199 {6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}},
200 {7,'-','X','!','!',O_XCH|O_UNSZ,"xch",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}},
474 {44,'-','B','S','S',O_SCB_NE|O_UNSZ,"scb/ne",2,{RS,PCREL8},3, {{0x06,0xff,0 },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}},
475 {45,'-','B','S','S',O_SCB_F|O_UNSZ,"scb/f",2,{RS,PCREL8},3, {{0x01,0xff,0 },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}},
476 {46,'-','B','S','S',O_SCB_EQ|O_UNSZ,"scb/eq",2,{RS,PCREL
[all...]
H A Di370-opc.c143 /* The R1 register field in an RX or RS form instruction. */
168 /* The D2 displacement field in an RS form instruction. */
171 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},
173 /* The R3 register field in an RS form instruction. */
176 { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },
178 /* The B2 base field in an RS form instruction. */
181 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},
183 /* The optional B2 base field in an RS form instruction. */
187 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},
365 /* An RS for
362 #define RS macro
[all...]
/netbsd-6-1-5-RELEASE/external/bsd/pcc/dist/pcc/f77/fcom/
H A Dscjdefs.h20 #define P2RSHIFT RS
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/mcore/
H A Dinterp.c749 #define RS ((inst >> 4) & 0xF) macro
882 switch RS
1086 switch RS
1167 cpu.gr[RD] = cpu.gr[RS];
1172 unsigned int t = cpu.gr[RS];
1181 cpu.gr[RD], cpu.gr[RS], cpu.gr[RD] * cpu.gr[RS]);
1182 cpu.gr[RD] = cpu.gr[RD] * cpu.gr[RS];
1191 --cpu.gr[RS]; /* not RD! */
1192 NEW_C (((long)cpu.gr[RS]) >
[all...]
/netbsd-6-1-5-RELEASE/external/bsd/pcc/dist/pcc/cc/cpp/
H A Dcpy.y86 %term EQ NE LE GE LS RS
101 %left LS RS
132 | e RS e
/netbsd-6-1-5-RELEASE/distrib/utils/sysinst/arch/ofppc/
H A Dmsg.md.en78 {You need to have two PReP partitions to boot an IBM RS/6000. One needs to
84 least 1KB, and 1MB in size. IBM RS/6000 machines generally need the PReP
H A Dmsg.md.es79 {You need to have two PReP partitions to boot an IBM RS/6000. One needs to
85 least 1KB, and 1MB in size. IBM RS/6000 machines generally need the PReP
/netbsd-6-1-5-RELEASE/sys/arch/x68k/include/
H A Dkbdmap.h36 #define RS 30 macro
/netbsd-6-1-5-RELEASE/sys/arch/x68k/usr.bin/loadkmap/
H A Dkbdmap.h33 #define RS 30 macro
/netbsd-6-1-5-RELEASE/sys/arch/atari/dev/
H A Dkbdmap.h66 #define RS 30 macro
/netbsd-6-1-5-RELEASE/sys/arch/amiga/dev/
H A Dkbdmap.h62 #define RS 30 macro
/netbsd-6-1-5-RELEASE/usr.sbin/lpr/common_source/
H A Dlp.h67 extern long RS; /* restricted to those with local accounts */
/netbsd-6-1-5-RELEASE/external/bsd/pcc/dist/pcc/cc/ccom/
H A Doptim.c161 case RS:
167 if (LO(p) == RS && RCON(p->n_left) && RCON(p) &&
218 else if (LO(p) == RS && RCON(p->n_left) && RCON(p)) {
226 p->n_op = RS;
356 p->n_op = RS;
403 q->n_op = RS;

Completed in 495 milliseconds

1234