/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/opcodes/ |
H A D | m88k-dis.c | 40 {0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} }, 41 {0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} }, 42 {0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} }, 43 {0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0,1,0,0,0,1,1,0,0,0,0} }, 48 {0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, 49 {0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, 50 {0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, 51 {0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, 52 {0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0,0,0,1,0,0,0,0} }, 53 {0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{ [all...] |
H A D | cr16-opc.c | 460 REG(u4, 0x84, CR16_U_REGTYPE) 463 #define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} macro 469 #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE) 475 REG(r12_L, 12, CR16_R_REGTYPE), 476 REG(r13_L, 13, CR16_R_REGTYPE), 477 REG(ra, 0xe, CR16_R_REGTYPE), 478 REG(sp, 0xf, CR16_R_REGTYPE), 479 REG(sp_L, 0xf, CR16_R_REGTYPE), 480 REG(RA, 0xe, CR16_R_REGTYPE), 491 REG((r1 [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/opcodes/ |
H A D | m88k-dis.c | 40 {0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} }, 41 {0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} }, 42 {0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} }, 43 {0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0,1,0,0,0,1,1,0,0,0,0} }, 48 {0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, 49 {0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, 50 {0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, 51 {0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, 52 {0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0,0,0,1,0,0,0,0} }, 53 {0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{ [all...] |
H A D | cr16-opc.c | 460 REG(u4, 0x84, CR16_U_REGTYPE) 463 #define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} macro 469 #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE) 475 REG(r12_L, 12, CR16_R_REGTYPE), 476 REG(r13_L, 13, CR16_R_REGTYPE), 477 REG(ra, 0xe, CR16_R_REGTYPE), 478 REG(sp, 0xf, CR16_R_REGTYPE), 479 REG(sp_L, 0xf, CR16_R_REGTYPE), 480 REG(RA, 0xe, CR16_R_REGTYPE), 491 REG((r1 [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.dg/ |
H A D | pr31866.c | 6 # define REG "$1" macro 8 # define REG "r10" macro 10 # define REG "%eax" macro 12 # define REG "$8" macro 15 # define REG "6" macro 17 # define REG "rax" macro 25 register long int r asm (REG) = a;
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H A D | pr16194.c | 6 #define ASMDECL __asm (REG); 7 #define CLOBBER_LIST : REG 10 # define REG "$1" macro 12 # define REG "r10" macro 14 # define REG "%r10" macro 16 # define REG "%eax" macro 18 # define REG "$8" macro 21 # define REG "6" macro 23 # define REG "rax" macro 25 # define REG " macro [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/ld/testsuite/ld-mmix/ |
H A D | greg-6.d | 44 0+20 l \*REG\* 0+ P 45 0+21 l \*REG\* 0+ O 46 0+22 l \*REG\* 0+ N 47 0+23 l \*REG\* 0+ M 48 0+24 l \*REG\* 0+ L 49 0+25 l \*REG\* 0+ K 50 0+26 l \*REG\* 0+ J 51 0+27 l \*REG\* 0+ I 52 0+28 l \*REG\* 0+ H 53 0+29 l \*REG\* [all...] |
H A D | greg-7.d | 44 0+21 l \*REG\* 0+ P 45 0+22 l \*REG\* 0+ O 46 0+23 l \*REG\* 0+ N 47 0+24 l \*REG\* 0+ M 48 0+25 l \*REG\* 0+ L 49 0+26 l \*REG\* 0+ K 50 0+27 l \*REG\* 0+ J 51 0+28 l \*REG\* 0+ I 52 0+29 l \*REG\* 0+ H 53 0+2a l \*REG\* [all...] |
/netbsd-6-1-5-RELEASE/sys/arch/sh3/sh3/ |
H A D | devreg.c | 103 SH ## x ## REG(TRA); \ 104 SH ## x ## REG(EXPEVT); \ 105 SH ## x ## REG(INTEVT); \ 107 SH ## x ## REG(BARA); \ 108 SH ## x ## REG(BAMRA); \ 109 SH ## x ## REG(BASRA); \ 110 SH ## x ## REG(BBRA); \ 111 SH ## x ## REG(BARB); \ 112 SH ## x ## REG(BAMRB); \ 113 SH ## x ## REG(BASR [all...] |
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/testsuite/gcc.dg/ |
H A D | pr16194.c | 5 #define ASMDECL __asm (REG); 6 #define CLOBBER_LIST : REG 9 # define REG "$1" macro 11 # define REG "r10" macro 13 # define REG "%eax" macro 15 # define REG "$8" macro 18 # define REG "6" macro 20 # define REG "rax" macro 25 # define REG "conflict" macro 50 __asm__ ("":"=g"(*dst): : REG); /* { d [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/include/opcode/ |
H A D | i960.h | 40 #define REG 3 macro 50 /* Masks for the mode bits in REG format instructions */ 55 /* Generate the 12-bit opcode for a REG format instruction by placing the 62 /* Generate a template for a REG format instruction: place the opcode bits 70 * The information is also useful to us because some 1-operand REG instructions 71 * use the src1 field, others the dst field; and some 2-operand REG instructions 139 char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ 284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, 285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, 286 { R_3(0x582), "andnot", I_BASE, REG, [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/include/opcode/ |
H A D | i960.h | 40 #define REG 3 macro 50 /* Masks for the mode bits in REG format instructions */ 55 /* Generate the 12-bit opcode for a REG format instruction by placing the 62 /* Generate a template for a REG format instruction: place the opcode bits 70 * The information is also useful to us because some 1-operand REG instructions 71 * use the src1 field, others the dst field; and some 2-operand REG instructions 139 char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ 284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, 285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, 286 { R_3(0x582), "andnot", I_BASE, REG, [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.target/i386/ |
H A D | pr36753.c | 5 #define REG "edi" macro 7 #define REG "r14" macro 10 register unsigned long *ds asm(REG);
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/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.dg/tree-ssa/ |
H A D | 20030714-1.c | 8 REG, enumerator in enum:rtx_code 26 if ((src_0->code == REG) && (({src_2;})->frame_related)) 28 if ((src_1->code == REG) && (({ src_3;})->frame_related)) 30 if (src_0->code == REG) 32 if (src_1->code == REG)
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/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/testsuite/gcc.dg/tree-ssa/ |
H A D | 20030714-1.c | 8 REG, enumerator in enum:rtx_code 26 if ((src_0->code == REG) && (({src_2;})->frame_related)) 28 if ((src_1->code == REG) && (({ src_3;})->frame_related)) 30 if (src_0->code == REG) 32 if (src_1->code == REG)
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/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/config/ |
H A D | rx-parse.y | 135 %type <regno> REG FLAG CREG BCND BMCND SCCND 139 %token REG FLAG CREG 269 | MOV DOT_B '#' EXPR ',' disp '[' REG ']' 277 | MOV DOT_W '#' EXPR ',' disp '[' REG ']' 283 | MOV DOT_L '#' EXPR ',' disp '[' REG ']' 291 | RTSD '#' EXPR ',' REG '-' REG 300 | CMP REG ',' REG 305 | CMP disp '[' REG ']' DOT_U [all...] |
H A D | bfin-parse.y | 471 %token REG 598 %type <reg> REG 795 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN 825 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG 826 COLON expr COMMA REG COLON expr RPAREN aligndir 841 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLO [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/testsuite/gas/mmix/ |
H A D | save-op.l | 16 \*REG\*:000000000000001f X 17 \*REG\*:0000000000000000 X0
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H A D | unsave-op.l | 16 \*REG\*:000000000000001f X 17 \*REG\*:0000000000000000 X0
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H A D | reg-op.l | 23 \*REG\*:0000000000000017 X 24 \*REG\*:000000000000000c Y 25 \*REG\*:0000000000000043 Z
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H A D | roundr-op.l | 20 \*REG\*:0000000000000087 X 21 \*REG\*:00000000000000f4 Z
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H A D | set.l | 19 \*REG\*:000000000000001f X 20 \*REG\*:0000000000000075 Y
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/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/alpha/ |
H A D | vms-gcc_shell_handler.c | 38 typedef unsigned long long REG; typedef 40 #define REG_AT(addr) (*(REG *)(addr)) 57 get_dyn_handler_pointer (REG fp) 69 REG handler_slot_offset; 74 REG handler_data_offset; 100 handler_slot_offset = REG_AT ((REG)pd + handler_data_offset);
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/netbsd-6-1-5-RELEASE/usr.sbin/gspa/gspa/ |
H A D | gsp_inst.c | 99 #define EXREG (REG|EXPR) 100 #define EAREG (REG|EA) 101 #define EXAREG (REG|EXPR|EA) 104 #define OPTREG (OPTOPRN|REG) 126 {"ABS", 0x0380, ONEREG, {REG, 0, 0, 0}}, 127 {"ADD", 0x4000, ADD, {EXREG, REG, OPTSPEC,0}}, 128 {"ADDC",0x4200, TWOREG, {REG, REG, 0, 0}}, 129 {"ADDI",0x0B20, IMMREG, {EXPR, REG, OPTSPEC,0}}, 130 {"ADDK",0x1000, K32REG, {EXPR, REG, [all...] |
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/ppc/ |
H A D | idecode_expression.h | 270 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL) 271 #define CR_FIELD(REG) EXTRACTED32(CR, REG*4, REG*4+3) 272 #define CR_SET_XER_SO(REG, VAL) \ 277 CR_SET(REG, new_bits); \ 280 #define CR_COMPARE(REG, LHS, RHS) \ 285 CR_SET(REG, new_bit [all...] |