Searched refs:P2 (Results 1 - 25 of 99) sorted by relevance

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/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/opcodes/
H A Dia64-opc-a.c151 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
152 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
153 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
154 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
155 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
156 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
157 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
158 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
159 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
160 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R
[all...]
H A Dtic80-opc.c563 /* The 'P2' field at bits 8-7 in floating point instructions */
564 #define P2(x) ((x) << 7)
777 {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
778 {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
779 {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
780 {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(
561 #define P2 macro
[all...]
H A Dia64-opc-f.c90 {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY},
91 {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL},
92 {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY},
93 {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY},
94 {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY},
96 {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY},
97 {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL},
98 {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY},
99 {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY},
100 {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/opcodes/
H A Dia64-opc-a.c151 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
152 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
153 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
154 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
155 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
156 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
157 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
158 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
159 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
160 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R
[all...]
H A Dtic80-opc.c563 /* The 'P2' field at bits 8-7 in floating point instructions */
564 #define P2(x) ((x) << 7)
777 {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
778 {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
779 {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
780 {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(
561 #define P2 macro
[all...]
H A Dia64-opc-f.c90 {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY},
91 {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL},
92 {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY},
93 {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY},
94 {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY},
96 {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY},
97 {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL},
98 {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY},
99 {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY},
100 {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/frv/
H A Dfrv-asm.h22 P2(INSN): Emit INSN.P on the FR500 and above, otherwise emit plain INSN. */
30 #define P2(A) P(A) macro
32 #define P2(A) A macro
36 #define P2(A) A macro
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/config/frv/
H A Dfrv-asm.h23 P2(INSN): Emit INSN.P on the FR500 and above, otherwise emit plain INSN. */
31 #define P2(A) P(A) macro
33 #define P2(A) A macro
37 #define P2(A) A macro
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/testsuite/gas/bfin/
H A Dflow.s59 P2 = P0 << 2; define
60 P2 = P2 + FP; define
63 P2 = P2 + P1; define
65 [P2] = R0;
95 P2 = P0 << 2; define
96 P2 = P2 + FP; define
99 P1 = P2
102 P2 = P0 << 2; define
103 P2 = P2 + FP; define
106 P2 = P2 + P0; define
[all...]
H A Dcache2.s12 PREFETCH [ P2 ] ;
22 PREFETCH [ P2++ ] ;
32 FLUSH [ P2 ] ;
41 FLUSH [ P2++ ] ;
51 FLUSHINV [ P2 ] ;
61 FLUSHINV [ P2++ ] ;
71 IFLUSH [ P2 ] ;
81 IFLUSH [ P2++ ] ;
H A Dflow.d29 28: 72 00 CALL \(PC \+ P2\);
47 50: 42 44 P2 = P0 << 0x2;
48 52: ba 5a P2 = P2 \+ FP;
51 5a: 8a 5a P2 = P2 \+ P1;
53 5e: 10 93 \[P2\] = R0;
73 9e: 42 44 P2 = P0 << 0x2;
74 a0: ba 5a P2 = P2 \
[all...]
H A Dcontrol_code2.s75 CC = P0 == P2;
82 CC = P2 == -4;
83 CC = P2 == 0;
84 CC = P2 == 3;
89 CC = P0 < P2;
96 CC = P2 < -4;
97 CC = P2 < 0;
98 CC = P2 < 3;
104 CC = P0 <= P2;
111 CC = P2 <
[all...]
H A Dcache2.d9 4: 42 02 PREFETCH\[P2\];
17 14: 62 02 PREFETCH\[P2\+\+\];
25 24: 52 02 FLUSH\[P2\];
33 34: 72 02 FLUSH\[P2\+\+\];
41 44: 4a 02 FLUSHINV\[P2\];
49 54: 6a 02 FLUSHINV\[P2\+\+\];
57 64: 5a 02 IFLUSH\[P2\];
65 74: 7a 02 IFLUSH\[P2\+\+\];
H A Dexpected_errors.s59 [ R0 ++ P2 ] = R2;
62 [ I0 ++ P2 ] = R2;
66 W [ R0 ++ P2 ] = R2.h;
69 W [ I0 ++ P2 ] = R2.h;
72 [ I0 ++ ] = P2;
75 W [ I0 ++ ] = P2.h;
79 W [ P0 ++ ] = P2;
83 B [ P0 ++ ] = P2;
87 R2 = [ R0 ++ P2 ];
90 R2 = [ I0 ++ P2 ];
100 P2 = [ I0 ++ ]; define
111 P2 = W [ P0 ++ ] (X); define
115 P2 = B [ P0 ++ ] (X); define
[all...]
H A Dstore.d10 6: d6 bf \[P2 \+ 0x3c\] = SP;
12 c: 3a bc \[FP \+ 0x0\] = P2;
17 12: 10 93 \[P2\] = R0;
42 40: 13 97 W\[P2\] = R3;
46 48: 56 e6 ff 7f W\[P2 \+ 0xfffe\] = R6;
48 50: 56 8b W\[SP \+\+ P2\] = R5.L;
54 58: 97 e6 19 00 B\[P2 \+ 0x19\] = R7;
H A Dparallel2.s51 r7.l = r0.L << 0 || R5 = W [P2] (z);
52 r5 = r5 >> 31 || R7 = W [P2++] (z);
53 r0 = r0 << 12 || R5 = W [P2--] (z);
54 A0 = A0 >> 1 || R5 = W [P2+0] (z);
55 A0 = A0 << 0 || R5 = W [P2+2] (z);
56 a1 = A1 << 31 || R5 = W [P2+4] (z);
57 a1 = a1 >> 16 || R5 = W [P2+30] (z);
59 R1.H = LShift r2.h by r0.l || R5 = W [P2+24] (z);
60 r0.l = LSHIFT r0.h by r1.l || R5 = W [P2+22] (z);
61 r7.L = lshift r6.L BY r2.l || R5 = W [P2
[all...]
H A Devent2.s36 TESTSET (P2);
H A Dshift2.s12 P2 = (P2+P0)<<1; define
13 P1 = (P1+P2)<<1;
15 //P0 = (P2+P0)<<1;
20 P2 = (P2+P0)<<2; define
21 P1 = (P1+P2)<<2;
23 //P0 = (P2+P0)<<2;
45 P0 = P0 + (P2 << 1);
46 P0 = P1 + (P2 <<
[all...]
H A Dloop_temps.s79 P2 = P1 << 2; define
80 SP -= P2;
150 P2 = P1 << 2; define
151 SP -= P2;
178 P2 = R0; define
179 R0 = W [P2] (Z);
192 P2 = R0; define
193 R0 = W [P2] (Z);
208 P2 = [FP+-16]; define
209 I2 = P2;
281 P2 = I2; define
[all...]
H A Dcontrol_code2.d52 5a: 50 08 CC = P0 == P2;
57 64: 62 0c CC = P2 == -0x4;
58 66: 42 0c CC = P2 == 0x0;
59 68: 5a 0c CC = P2 == 0x3;
62 6e: d0 08 CC = P0 < P2;
67 78: e2 0c CC = P2 < -0x4;
68 7a: c2 0c CC = P2 < 0x0;
69 7c: da 0c CC = P2 < 0x3;
72 82: 50 09 CC = P0 <= P2;
77 8c: 62 0d CC = P2 <
[all...]
H A Dparallel2.d96 160: 80 ce 00 8e R7.L = R0.L << 0x0 \|\| R5 = W\[P2\] \(Z\) \|\| NOP;
98 168: 82 ce 0d 8b R5 = R5 >> 0x1f \|\| R7 = W\[P2\+\+\] \(Z\) \|\| NOP;
100 170: 82 ce 60 80 R0 = R0 << 0xc \|\| R5 = W\[P2--\] \(Z\) \|\| NOP;
102 178: 83 ce f8 41 A0 = A0 >> 0x1 \|\| R5 = W\[P2 \+ 0x0\] \(Z\) \|\| NOP;
104 180: 83 ce 00 00 A0 = A0 << 0x0 \|\| R5 = W\[P2 \+ 0x2\] \(Z\) \|\| NOP;
106 188: 83 ce f8 10 A1 = A1 << 0x1f \|\| R5 = W\[P2 \+ 0x4\] \(Z\) \|\| NOP;
108 190: 83 ce 80 51 A1 = A1 >> 0x10 \|\| R5 = W\[P2 \+ 0x1e\] \(Z\) \|\| NOP;
110 198: 00 ce 02 b2 R1.H = LSHIFT R2.H BY R0.L \|\| R5 = W\[P2 \+ 0x18\] \(Z\) \|\| NOP;
112 1a0: 00 ce 08 90 R0.L = LSHIFT R0.H BY R1.L \|\| R5 = W\[P2 \+ 0x16\] \(Z\) \|\| NOP;
114 1a8: 00 ce 16 8e R7.L = LSHIFT R6.L BY R2.L \|\| R5 = W\[P2 \
[all...]
H A Dcache.d12 6: 52 02 FLUSH\[P2\];
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.c-torture/execute/
H A Dva-arg-24.c41 #define P2 P(2) macro
71 TCASE(2, p0 p1 p2 , P0 P1 P2 )
72 TCASE(3, p0 p1 p2 p3 , P0 P1 P2 P3 )
73 TCASE(4, p0 p1 p2 p3 p4 , P0 P1 P2 P3 P4 )
74 TCASE(5, p0 p1 p2 p3 p4 p5 , P0 P1 P2 P3 P4 P5 )
75 TCASE(6, p0 p1 p2 p3 p4 p5 p6 , P0 P1 P2 P3 P4 P5 P6 )
76 TCASE(7, p0 p1 p2 p3 p4 p5 p6 p7 , P0 P1 P2 P3 P4 P5 P6 P7 )
77 TCASE(8, p0 p1 p2 p3 p4 p5 p6 p7 p8 , P0 P1 P2 P3 P4 P5 P6 P7 P8 )
78 TCASE(9, p0 p1 p2 p3 p4 p5 p6 p7 p8 p9, P0 P1 P2 P3 P4 P5 P6 P7 P8 P9)
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/testsuite/gcc.c-torture/execute/
H A Dva-arg-24.c41 #define P2 P(2) macro
71 TCASE(2, p0 p1 p2 , P0 P1 P2 )
72 TCASE(3, p0 p1 p2 p3 , P0 P1 P2 P3 )
73 TCASE(4, p0 p1 p2 p3 p4 , P0 P1 P2 P3 P4 )
74 TCASE(5, p0 p1 p2 p3 p4 p5 , P0 P1 P2 P3 P4 P5 )
75 TCASE(6, p0 p1 p2 p3 p4 p5 p6 , P0 P1 P2 P3 P4 P5 P6 )
76 TCASE(7, p0 p1 p2 p3 p4 p5 p6 p7 , P0 P1 P2 P3 P4 P5 P6 P7 )
77 TCASE(8, p0 p1 p2 p3 p4 p5 p6 p7 p8 , P0 P1 P2 P3 P4 P5 P6 P7 P8 )
78 TCASE(9, p0 p1 p2 p3 p4 p5 p6 p7 p8 p9, P0 P1 P2 P3 P4 P5 P6 P7 P8 P9)
/netbsd-6-1-5-RELEASE/external/lgpl3/mpfr/dist/
H A Dconst_catalan.c59 mpz_t T2, P2, Q2; local
62 mpz_init (P2);
64 S (T2, P2, Q2, m, n2);
68 mpz_mul (P, P, P2);
71 mpz_clear (P2);

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