Searched refs:OPCODE (Results 1 - 21 of 21) sorted by relevance

/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/opcodes/
H A Dspu-opc.c36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
H A Davr-dis.c40 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
H A Darc-dis.c64 #define OPCODE(word) (BITS ((word), 27, 31)) macro
562 state->_opcode = OPCODE (state->words[0]);
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/opcodes/
H A Dspu-opc.c36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
H A Davr-dis.c40 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
H A Darc-dis.c64 #define OPCODE(word) (BITS ((word), 27, 31)) macro
562 state->_opcode = OPCODE (state->words[0]);
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/config/mips/
H A Dmips16.S58 #define SFOP(NAME, OPCODE) \
64 OPCODE $f0,$f0,$f2; \
84 #define SFOP2(NAME, OPCODE) \
89 OPCODE $f0,$f0; \
110 #define SFCMP(NAME, OPCODE, TRUE, FALSE) \
114 OPCODE $f0,$f2; \
124 #define SFREVCMP(NAME, OPCODE, TRUE, FALSE) \
128 OPCODE $f2,$f0; \
234 #define DFOP(NAME, OPCODE) \
240 OPCODE
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/mips/
H A Dmips16.S79 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
80 #define DELAYt(T, OPCODE, OP2) \
83 OPCODE, OP2; \
86 /* Use "OPCODE. OP2" and jump to T. */
87 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
188 performs FPU operation OPCODE on them, and returns the single-
191 #define OPSF3(NAME, OPCODE) \
195 OPCODE RET,ARG1,ARG2; \
213 performs FPU operation OPCODE o
[all...]
H A Dmips.h2608 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2610 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2611 "%*" OPCODE "%?\t" OPERANDS "%/"
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/include/opcode/
H A Dspu.h72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
H A Dh8300.h619 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
626 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
627 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
628 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IG
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/include/opcode/
H A Dspu.h72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
H A Dh8300.h619 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
626 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
627 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
628 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IG
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/config/
H A Dtc-rx.c1558 #define OPCODE(type,size) ((type) * 16 + (size))
1630 switch (OPCODE (rx_opcode_type (fragP->fr_opcode), fragP->fr_subtype))
1632 case OPCODE (OT_bra, 1): /* BRA.S - no change. */
1635 case OPCODE (OT_bra, 2): /* BRA.B - 8 bit. */
1641 case OPCODE (OT_bra, 3): /* BRA.W - 16 bit. */
1653 case OPCODE (OT_bra, 4): /* BRA.A - 24 bit. */
1668 case OPCODE (OT_beq, 1): /* BEQ.S - no change. */
1671 case OPCODE (OT_beq, 2): /* BEQ.B - 8 bit. */
1677 case OPCODE (OT_beq, 3): /* BEQ.W - 16 bit. */
1689 case OPCODE (OT_be
1557 #define OPCODE macro
1941 #undef OPCODE macro
[all...]
H A Dtc-spu.c28 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
29 { MACFORMAT, (OPCODE) << (32-11), MNEMONIC, ASMFORMAT },
30 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
31 { MACFORMAT, ((OPCODE) << (32-11)) | ((FB) << (32-18)), MNEMONIC, ASMFORMAT },
H A Dtc-avr.c37 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
H A Dtc-hppa.c554 /* handle of the OPCODE hash table */
1012 /* Insert FIELD into OPCODE starting at bit START. Continue pa_ip
1015 #define INSERT_FIELD_AND_CONTINUE(OPCODE, FIELD, START) \
1017 ((OPCODE) |= (FIELD) << (START)); \
/netbsd-6-1-5-RELEASE/sys/arch/ia64/disasm/
H A Ddisasm_int.h59 #define OPCODE(i) FIELD(i, 37, 4) macro
H A Ddisasm_decode.c58 switch((int)OPCODE(bits)) {
545 switch((int)OPCODE(bits)) {
652 switch((int)OPCODE(bits)) {
898 if ((int)OPCODE(bits) >= 8)
902 switch((int)OPCODE(bits)) {
1274 if ((int)OPCODE(bits) >= 8)
1278 switch((int)OPCODE(bits)) {
2436 switch((int)OPCODE(bits)) {
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/microblaze/
H A Dinterp.c577 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
649 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/testsuite/gas/i386/
H A Dx86-64-opcode.s3 # O16 A32 OV REX OPCODE ; NOTES

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