Searched refs:NV04_PFIFO_CACHE1_DMA_CTL (Results 1 - 5 of 5) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/external/bsd/drm/dist/shared-core/
H A Dnv04_fifo.c112 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
113 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnv10_fifo.c129 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
130 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnv40_fifo.c142 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
143 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnouveau_fifo.c138 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
H A Dnouveau_reg.h516 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 macro

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